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參數(shù)資料
| 型號： | TAS5000PFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, TQFP-48 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 108K |
| 代理商： | TAS5000PFBG4 |
2–2
Table 2–1. Oscillator, External Clock, and PLL Functions
DESCRIPTION
M_S
DBSPD
XTL_IN
(MHz)
MCLK_IN
(MHz)
SCLK
(MHz)
LRCLK
(kHz)
MCLK_OUT
(MHz)#
Master, normal speed
1
0
11.2896
—
2.8224
44.1
11.2896
Master, normal speed
1
0
12.288
—
3.072
48
12.288
Master, double speed
1
—
22.5792§
5.6448
88.2
22.5792
Master, double speed
1
—
24.576§
6.144
96
24.576
Slave, normal speed
0
—
11.2896§
2.8224
44.1
Digital GND
0
—
12.288§
3.072
48
Digital GND
Slave, double speed
0
1
—
22.5792§
5.6448
88.2
Digital GND
Slave, double speed
0
1
—
24.576§
6.144
96
Digital GND
Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN.
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided.
§ External MCLK connected to MCLK_IN input
SCLK and LRCLK are outputs when M_S=1, inputs when M_S=0.
# MCLK_OUT is driven low when M_S=0.
2.5
Digital Interpolation Filter
The 24-bit high performance linear phase FIR interpolation filter up-samples the input digital data at a rate of 4 times
(double speed mode = 88.2 kHz or 96 kHz) or 8 times (normal mode = 44.1 kHz or 48 kHz) the incoming sample rate.
This filter provides very low pass-band ripple and optimized time domain transient response for accurate music
reproduction.
2.6
Digital PWM Modulator
The interpolation filter output is sent to the modulator. This modulator consists of a high performance 4th order digital
noise shaper and a PCM to PWM converter. Following the noise shaper, the PCM signal is fed into a very low distortion
PCM to PWM conversion block, buffered and output from the chip. The modulation scheme is based on a 2-state
control of the H-bridge output.
2.7
Control, Status, and Operational Modes
The TAS5000 control section consists of several control-input pins. Three serial mode pins (MOD0, MOD1, and
MOD2) are provided to select various serial data formats. During normal operating conditions if any of the MOD0,
MOD1, or MOD2 pins changes state, a reset sequence is initiated (see paragraph 2.7.2). Also provided are separate
power-down (PDN), reset (RESET), and mute (MUTE) pins. The ERR pin indicates that an error has occurred.
2.7.1
Power Up
At power up the ERR pin is asserted low and the PWM outputs go to the hard mute state in which the P outputs are
held low and the M outputs are held high. Following initialization, the TAS5000 will come up in the operational state.
There are two cases of power-up timing. The first case is shown in Figure 2–1 with RESET preceding PDN. The
second case is shown in Figure 2–2 with PDN preceding RESET.
Initialization Time = 4224 LRCLK Periods
RESET
ERR
PDN
Figure 2–1. Power-Up Timing (RESET preceding PDN)
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