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參數(shù)資料
| 型號： | TAS5000PFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, TQFP-48 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 108K |
| 代理商： | TAS5000PFBG4 |
3–2
3.3
Electrical Characteristics
3.3.1
Static Digital Specifications
(TA = 25°C; DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, AVDD1 = AVDD2 = 3.3 V ±10%)
MIN
MAX
UNIT
VIH
High-level input voltage
2
DVDD1
V
VIL
Low-level input voltage
0
0.8
V
VOH
High-level output voltage, (IO = –1 mA)
2.4
V
VOL
Low-level output voltage, (IO = 4 mA)
0.4
V
Input leakage current
–10
10
A
3.3.2
Digital Interpolation Filter and PWM Modulator
(TA = 25°C; DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, AVDD1 = AVDD2 = 3.3 V ±10%, Fs = 44.1 kHz)
All the terms characterized by frequency will scale with the normal mode sampling frequency, Fs.
MIN
TYP
MAX
UNIT
Pass band
0
20
kHz
Pass band ripple
±0.012
dB
Stop band
24.1
kHz
Stop band attenuation (24.1 kHz to 152.3 kHz)
50
dB
Group delay
700
S
PWM modulation index (gain)
0.93
3.3.3
TAS5000/TAS5100 System Performance Measured at the Speaker Terminals
Reference section 4.4 in the TAS5100 Data Manual
3.4
Switching Characteristics
3.4.1
Serial Audio Ports Slave Mode
(TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 3.3 V ±10%)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
SCLK frequency
6.144
MHz
tsu(SDIN)
SDIN setup time before SCLK rising edge
20
ns
th(SDIN)
SDIN hold time from SCLK rising edge
10
ns
F(LRCLK)
LRCLK frequency
44.1
48
96
kHz
MCLK duty cycle
50%
SCLK duty cycle
50%
LRCLK duty cycle
50%
tsu(LRCLK)
LRCLK edge setup before SCLK rising edge
20
ns
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