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參數(shù)資料
| 型號： | TAS5000PFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, TQFP-48 |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 108K |
| 代理商： | TAS5000PFBG4 |
2–3
Initialization Time = 256 LRCLK Periods
RESET
ERR
PDN
Greater Than 16 MCLK Periods
Figure 2–2. Power-Up Timing (PDN preceding RESET)
2.7.2
Reset
The reset signal for the TAS5000 should be applied whenever toggling the M_S, DBSPD signal. This reset is
asynchronous. See Figure 2–3 for reset timing. To initiate the reset sequence the RESET pin is asserted low. As long
as the pin is held low the chip is in the reset state. During this reset time the PWM outputs are hard-muted (P-outputs
held low and M-outputs held high) and the ERR status pin is held low. Assuming PDN is high, the rising edge of the
reset pulse begins chip initialization. After 256 LRCLK periods the TAS5000 will begin normal operation.
Initialization
Normal
Operation
RESET
ERR
PDN
Normal Operation
Figure 2–3. Reset Timing
2.7.3
Power Down
When PDN is low (see Figure 2–4. Power-Down Timing) both the PLL and the oscillator are shut down. Note that
power down is an asynchronous operation. To place the device in total power-down mode, both RESET and PDN
must be held low. As long as these pins are held low, the chip is in the power-down state and the PWM outputs are
hard muted with the P outputs held low and the M outputs held high. To place the device back into normal mode, see
section 2.7.1 for power-up timing.
NOTE: In order for the dynamic logic to be properly powered down, the clocks should not be stopped before
the PDN pin goes low. Otherwise, the device may drain additional supply current.
Initialization
Chip
Power-Down
ERR
PDN and
RESET
Normal Operation
Normal
Operation
Figure 2–4. Power-Down Timing
2.7.4
Mute
The TAS5000 provides a mute function that is used when the MUTE pin is asserted low. See Table 2–2 for Mute
Description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform in which
both sides of the differential PWM outputs have a 50% duty cycle.
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