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參數(shù)資料
| 型號(hào)： | TAS3001C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Stereo Audio Digital Equalizer |
| 中文描述： | 立體聲音頻數(shù)字均衡器 |
| 文件頁數(shù)： | 22/56頁 |
| 文件大小： | 417K |
| 代理商： | TAS3001C |
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32
3.2
Operation
To permit multiple devices to be controlled via the I
2
C bus, each slave device has an address. The TAS3001 has been
assigned four unique addresses to permit multiple TAS3001s to be used in a system. The addresses are selected
using the CS1 and CS2 pins. These four addresses, listed in Table 32, are licensed I
2
C addresses and do not conflict
with other licensed I
2
C audio devices. To communicate with the TAS3001, the I
2
C master must use the address
01101XX. In addition to the 7-bit device address, subaddresses are used to direct communication to the proper
memory location within the device. A complete table of subaddresses and control registers is provided in Appendix A,
Software Interface
.
Table 32. TAS3001 I
2
C Address
I2C ADDRESS BYTE
A6A2
CS2(A1)
CS1(A0)
R/W
68h
01101
0
0
0
6Ah
01101
0
1
0
6Ch
01101
1
0
0
6Eh
01101
1
1
0
3.2.1
Write Cycle Example
An example write cycle is demonstrated in Figure 32 and Table 33.
Start
Slave Address
R/W
A
Subaddress
A
Data Byte 1
A
Data Byte 1
A
Data Byte 2
A
Data Byte N
A
Stop
Figure 32. Write Cycle Example
Table 33. Write Cycle Example
FUNCTION
Start
Start condition as defined in I2C
Slave address
0110100 (CS1 = CS2 = 0)
R/W
0 (write)
A
Acknowledgement as defined in I2C (slave)
Subaddress
00000110 (see Appendix A,
Software Interface
)
Data
00011100 (see Appendix A,
Software Interface
)
Stop
Stop condition as defined in I2C
DESCRIPTION
Whenever writing to a subaddress, the correct number of data bytes must follow in order to complete the write cycle.
For example, if the volume control register with subaddress 04h is written to, six bytes of data must follow; otherwise,
the cycle will be incomplete and errors will occur.
I
2
C Timing and Wait Cycles
3.2.2
The TAS3001 issues I
2
C wait cycles to regulate the flow of command information. The TAS3001 can issue wait cycles
for each instruction. For any instruction, the TAS3001 can issue up to a one sample (23
μ
s) wait between data bytes
and between the last data byte and the I
2
C stop. This wait is generated after the acknowledgement. The duration of
this wait cycle is slightly longer than a sample interval, on the order of 1.1 x 1
÷
F
s
( or 25
μ
s at 44.1 kHz). This wait
cycle is illustrated in Figure 33.
Start
Slave Address
R/W
A
Subaddress
A
Data Byte 1
A
Wait
Data Byte 1
A
Wait
Data Byte 2
A
Wait
Data Byte N
A
Wait
Stop
Figure 33. Wait Cycle Example
The TAS3001 can also issue an I
2
C wait state after receiving an entire volume or tone command. The TAS3001
produces these wait cycles while it executes the interpolation algorithms from the present setting to the new setting.
The volume command always takes the same amount of time to process for a given sample rate. The treble and bass
commands vary depending upon the current index and the destination index. E.g., moving from 18 dB to 18 dB or
vice versa produces the longest wait.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS3001CPW | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3001CPWG4 | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3001CPWR | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3001CPWRG4 | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3001EVM | 制造商:Texas Instruments 功能描述:TAS3001 EVALUATION BOARD - Bulk |
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