參數(shù)資料
型號(hào)： TAS3001C
廠商： Texas Instruments, Inc.
英文描述： Stereo Audio Digital Equalizer
中文描述： 立體聲音頻數(shù)字均衡器
文件頁(yè)數(shù)： 21/56頁(yè)
文件大?。?/td> 417K
代理商： TAS3001C
31
3 Serial Control Interface (I
2
C)
The TAS3001 operation is controlled using the RESET signal and the serial control interface. Control information is
downloaded into the TAS3001 control registers by an I
2
C master device, such as a microprocessor, microcontroller,
or DSP. These registers control the settings for volume, bass, treble, mixing, and filtering. A description of the register
addresses and control formats is given in Appendix A.
The I
2
C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Each device is addressed by sending a unique 7-bit slave address plus an R/W bit (1 byte).
All I
2
C compatible devices are controlled using the SDA and SCL signals using a wire-ANDed connection. A pullup
resistor must be used to set the high level on the bus. The TAS3001 operates in standard I
2
C mode up to 100 kbps
with as many devices on the bus as desired up to the capacitance load limit of 400 pF.
The TAS3001 is an I
2
C slave-only device; therefore, at least one device connected to the I
2
C bus with this device
must operate in master mode. The pullup resistor is generally 4.99 k
. Upon power up, the I
2
C is in an unknown state
until the master clock has been applied and the TAS3001 has been reset. Prior to reset, the TAS3001 may hold the
SDA and/or SCL lines low. This creates I
2
C communication errors for any other device that attempts to use the bus.
3.1
I
2
C Protocol
The bus standard uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions.
A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 31. These start
and stop conditions for the I
2
C bus are required by standard protocol to be generated by the master. The master must
also generate the 7-bit slave address and the read/write (R/W) bit to open communication with another device and
then wait for an acknowledge condition. The slave holds SDA low during acknowledge clock period to indicate an
acknowledgment. When this occurs, the master transmits the next byte of the sequence.
After each 8-bit word, an acknowledgment must be transmitted by the receiving device. There is no limit on the
number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master
generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 31. Definitions
for the I
2
C protocol terms are listed in Table 31.
7 Bit Slave Address
R/W
8 Bit Subaddress (N)
A
A
8 Bit Data For
Address (N)
A
8 Bit Data For
Address (N)
A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Start
Stop
SDA
SCL
Figure 31. Typical I
2
C Data Transfer Sequence
Table 31. I
2
C Protocol Definitions
DEFINITION
DESCRIPTION
Master
The device that initiates a transfer, generates clock signals, and terminates the transfer
Receiver
The device that receives data
Slave
The device addressed by the master
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TAS3001CPW 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3001CPWG4 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3001CPWR 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3001CPWRG4 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3001EVM 制造商:Texas Instruments 功能描述:TAS3001 EVALUATION BOARD - Bulk
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