參數(shù)資料
型號: TAS3001C
廠商: Texas Instruments, Inc.
英文描述: Stereo Audio Digital Equalizer
中文描述: 立體聲音頻數(shù)字均衡器
文件頁數(shù): 14/56頁
文件大小: 417K
代理商: TAS3001C
18
1.12 Pin Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AVDD_PLL
AVSS_PLL
CAP_PLL
13
I
Analog power supply for the PLL
12
I
Analog ground for the PLL
C1 = 1500 pF // R1 = 27
+ C2 = 0.068
μ
F (recommended)
I2C address bit A0; low = 0, high = 1
I2C address bit A1; low = 0, high = 1
14
I
CS1
28
I
CS2
1
I
DVDD
DVSS
LRCLK
3
I
Digital power supply
2
I
Digital ground
I2S left/right clock sampling frequency (fs)
LRCLK generated from input MCLK (usually 256 fs) normally routed on PCB to pin 10
(LRCLK) as input fs sample clock.
Master clock (256 x fs)
10
I
LRCLKOUT
23
O
MCLK
9
I
NC
17, 18, 2022,
25, 26
Reserved No connection for normal operation
POWERDOWN
16
I
Powerdown input
RESET
19
I
Reset, high = normal operation, low = reinitialize the device
RESERVED
15, 27
Reserved digital ground for normal operation
Slave serial I2C clock
SCL
5
I/O
SCLK
11
I
Shift clock (bit clock)
SCLKOUT
24
O
SCLK generated from input MCLK (usually 256 fs) normally routed on PCB to pin 11 (SCLK)
as input 64 fs bit clock.
Slave serial I2C data
SDA
4
I/O
SDIN1
6
I
Serial audio data input one
SDIN2
7
I
Serial audio data input two
SDOUT
NOTE: Reset and other control functions require MCLK to be running. The system reset operation is a synchronous operation and requires a
minimum of four MCLK cycles to reset the device.
8
O
Serial audio data output
1.13 Ordering Information
TA
PACKAGE
SMALL OUTLINE (PW)
0
°
C to 70
°
C
TAS3001CPW
1.14 Power Supply
Digital supply voltage—DV
DD
, DV
SS
of 3.3 V
Analog supply voltage—AV
DD
PLL, AV
SS
PLL of 3.3 V
NOTE:
AV
DD
and AV
SS
for the PLL are derived from the digital supply and digital ground.
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