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參數(shù)資料
| 型號(hào)： | TAS3001C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Stereo Audio Digital Equalizer |
| 中文描述： | 立體聲音頻數(shù)字均衡器 |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 417K |
| 代理商： | TAS3001C |
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21
2 Audio Data Formats
2.1
Serial Audio Interface
The TAS3001 operates in digital audio slave mode only. The TAS3001 supports three serial audio data formats: I
2
S,
left-justified, and right-justified. Data word lengths of 16, 18, and 20 bits are supported.
Data is input into SDIN1 and SDIN2 under the influence of the master clock (MCLK), left/right clock (LRCLK), and
shift clock (SCLK) inputs.
Data is output on the SDOUT pin under the influence of the master clock (MCLK) input plus the left/right clock
(LRCLKOUT) and shift clock (SCLKOUT) outputs. LRCLKOUT and SCLKOUT are generated from the MCLK input
(usually at 256
×
f
s
). Typically these are routed on the PCB to LRCLK (as the input f
s
sample clock) and SCLK (as
the input 64
×
f
s
bit clock).
The TAS3001 device is compatible with 10 different serial interfaces. Available interface options are I
2
S,
right-justified, and left-justified. Table 21 and Table 22 indicate how the 10 options are selected using the I
2
C bus
and the main control register (MCR, I
2
C address 01h). All serial interface options at either 16, 18, or 20 bits operate
with SCLK at 64
×
f
s
. The 16-bit mode, left-justified, can operate at 32
×
f
s
or 64
×
f
s
.
Table 21. Serial Interface Input Options
MODE
MCR BIT 6
SC
MCR BITS 32
F(1,0)
MCR BITS 10
W(1,0)
SERIAL INTERFACE
SDIN1, SDIN2
0
0
00
00
16-bit, left-justified, 32
×
fs
16-bit, left-justified, 64
×
fs
16-bit, right-justified, 64
×
fs
16-bit, I2S, 64
×
fs
18-bit, left-justified, 64
×
fs
18-bit, right-justified, 64
×
fs
18-bit, I2S, 64
×
fs
20-bit, left-justified, 64
×
fs
20-bit, right-justified, 64
×
fs
20-bit, I2S, 64
×
fs
1
1
00
00
2
1
01
00
3
1
10
00
4
1
00
01
5
1
01
01
6
1
10
01
7
1
00
10
8
1
01
10
9
1
10
10
Table 22. Serial Interface Output Options
MODE
MCR BIT 6
SC
MCR BITS 54
E(1,0)
MCR BITS 10
W(1,0)
SERIAL INTERFACE
SDOUT
0
0
00
00
16-bit, left-justified, 32
×
fs
16-bit, left-justified, 64
×
fs
16-bit, right-justified, 64
×
fs
16-bit, I2S, 64
×
fs
18-bit, left-justified, 64
×
fs
18-bit, right-justified, 64
×
fs
18-bit, I2S, 64
×
fs
20-bit, left-justified, 64
×
fs
20-bit, right-justified, 64
×
fs
20-bit, I2S, 64
×
fs
1
1
00
00
2
1
01
00
3
1
10
00
4
1
00
01
5
1
01
01
6
1
10
01
7
1
00
10
8
1
01
10
9
1
10
10
Figure 21 through Figure 24 illustrate the relationship between the SCLK, LRCLK, and the serial data input and
output protocol options.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS3001CPW | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3001CPWG4 | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3001CPWR | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3001CPWRG4 | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3001EVM | 制造商:Texas Instruments 功能描述:TAS3001 EVALUATION BOARD - Bulk |
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