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參數(shù)資料
| 型號： | T90FJR-5VV |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, VQFP-128 |
| 文件頁數(shù)： | 9/42頁 |
| 文件大?。?/td> | 358K |
| 代理商： | T90FJR-5VV |
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17
4152B–ASSP–09/05
A/T90FJR
MOSTRTA, MOSTRB except for clock high and low times.
Delays for MOCLK, MDO, MOSTRT, MOVAL are also applicable to MICLKA, MICLKB, MDIA,
MDIB, MIVALA, MIVALB, MISTRTA, MISTRTB.
6.1.4.2
AC Electrical characteristics
VCC = 5V, T = 25°C
Note:
(1) for a clock period of 111 ns
7.
Command interface
The command interface is directly issued from PC Card standard [1] restricted to 8 bits access
and 15 bits addressing. The command interface of a CI module is described in detail in the PC
Card standard [1] and the restrictions applied to this standard for the command interface are
described in the DVB CI standard [2].
7.1
Command interface signals
The 15 address bits and 8 data bits of the CI module are connected to the host microprocessor
bus through buffers (type 373 and 245) which are controlled by the CIMaX. The CIMaX pro-
vides the buffers control signals:
DATOE#Data Output enable (active low)
ADOE# Address Output enable (active low)
DATDIR Data direction according to the read/write current cycle
ADLE Address Latch enable to latch the address bus until the end of the read/write cycle.
(see application note for connection of the buffers)
The buffers should be powered by the same source (voltage) as the modules.
The CI control signals are the same as the PC Card control signals : CE1#, CE2#, REG#, OE#,
WE#, IORD#, IOWR#, RDY/IRQ#, WAIT#. The CIMaX generates those signals so that they fit
Parameter
Min
Max
Unit
tclkip
MPEG input clock period
111
ns
tclkih
MICLK input clock high time
MOCLKA/B input clock high time
24
44
97
(1)
67
ns
tclkil
MICLK input clock low time
MOCLKA/B input clock low time
24
44
97
(1)
67
ns
tclkop
MPEG output clock period
111
ns
tclkoh
output clock high time
24
91
(1)
ns
tclkol
output clock low time
24
91
(1)
ns
tsu
input data setup
10
ns
th
input data hold
10
ns
tckd
clock to data delay
0
15
ns
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