參數(shù)資料
型號(hào)： T90FJR-5VV
廠商： ATMEL CORP
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： PLASTIC, VQFP-128
文件頁(yè)數(shù)： 25/42頁(yè)
文件大?。?/td> 358K
代理商： T90FJR-5VV
31
4152B–ASSP–09/05
A/T90FJR
9.
Module Detection & Activation
Common Interface modules are hot-plugable. In order to achieve this function, the CIMaX
automatically detects the insertion and removal of a module and acts as programmed whenever
this occurs.
In order to detect a module, the PC Card standard defines two reserved pins on the connector:
CD1# and CD2#. They must be simultaneously asserted (grounded) to ensure a module is
inserted. When a module is inserted, the CIMaX can automatically activate the module if pro-
grammed so when AUTO bit is asserted in the Module Control Register and VCC bit is set in the
Power Control Register (modules VCC is on). The activation can also be handled manually by
the host microprocessor by sequentially asserting the right bits in the Module Control Register. If
both modules are inserted simultaneously, autoactivation procedure is performed sequentially
on one module after the other.
The module activation consists in resetting the module and waiting for RDY signal to go high
with respect to the PC Card standard timings.
9.1
Interrupts
Interrupts are managed by CIMaX and one interrupt output is available for connecting
CIMaX to the main microprocessor interrupt controller. Five interrupt sources are available :
modules detection (2) modules IRQ (2) and one external device interrupt applied to the CIMaX
by using the external interrupt input pin. Modules detection interrupts are latched inside the
CIMaX and are acknowledged on the reading of the Interrupt Status Register. Each interrupt
source can be individually masked. When masked, an incoming interrupt is visible in the Inter-
rupt Status Register but does not generate an interrupt to the host microprocessor. The INT
output to the host microprocessor can be configured to be active high or low and driven by a
push-pull or an open drain.
Symbol
Min
Max
Unit
t
h (Hi-z)
Card detect to reset driven
300
ms
t
w (RESET)
Reset pulse width
11
s
t
busy
Reset asserted to ready negated
(informative)
10
s
t
rdy
Reset negated to module ready
(informative)
5s
t
h (Hi-z)
t
W (RESET)
t
rdy
CD1,2#
RESET
RDY/IRQ#
t
busy
t
h (Hi-z)
t
W (RESET)
t
rdy
CD1,2#
RESET
RDY/IRQ#
t
busy
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