參數(shù)資料
型號: T90FJR-5VV
廠商: ATMEL CORP
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝: PLASTIC, VQFP-128
文件頁數(shù): 42/42頁
文件大?。?/td> 358K
代理商: T90FJR-5VV
9
4152B–ASSP–09/05
A/T90FJR
The input signals from the host microprocessor are combined, depending on the host micropro-
cessor configuration, to form a read and write signal RD’ and WR’. These signals indicate an
active read or write cycle in process.
Figure 5-2.
Read access
Notes:
1. The WAIT/ACK output is either WAIT or ACK formatted according to the WAIT/ACK pin set-
tings (active level, driving structure).
2. Depending on the read access type, CE can be either CE1A# or CE1B# for access to memory
or IO to module A or B, CE2A# or CE2B# for access in EC (Extended Channel) mode, or even
EXTCS for access to external device in regenerate mode.
3. REG# signal is not asserted during a common memory or external access.
4. OE# signal is asserted during a memory access (attribute or common). It is replaced by
IORD# during an IO read cycle, an EC (Extended Channel) read cycle (using CE2A# or
CE2B#) or an external access in regenerate mode.
5. t4 can be lengthened by the insertion of wait cycles. When the destination module asserts
WAIT# signal, the t4 cycles counter stops until WAIT# becomes inactive anew.
Memory read timings are given for various cycle duration. In attribute memory mode, only 600ns
and 300ns cycles are available. In common memory mode, 300ns doesn’t exist. IO and external
device in regenerate mode share the same timing specifications as they all use IORD# and
IOWR# signals. Timings are given in CIMaX clock cycles. They are calculated to comply with
PCMCIA specifications when 27MHz clock is used.
t7
RD’
WAIT(1)
ACK(1)
CE(2)
REG#(3)
OE#(4)
ADLE
DATDIR
DATOE#
t1
t3
t4(5)
t6
t0
t5
t8
t10
t9
t2
t7
RD’
WAIT(1)
ACK(1)
CE(2)
REG#(3)
OE#(4)
ADLE
DATDIR
DATOE#
t1
t3
t4(5)
t6
t0
t5
t8
t10
t9
t2
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