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參數(shù)資料
| 型號(hào)： | T90FJR-5VV |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, VQFP-128 |
| 文件頁數(shù)： | 40/42頁 |
| 文件大?。?/td> | 358K |
| 代理商： | T90FJR-5VV |
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7
4152B–ASSP–09/05
A/T90FJR
Notations:
TTL: TTL level
CMOS:CMOS level
TS:
Tristate
trig:
Schmitt Trigger
up:
internal pull-up
down:internal pull-down
5.
Host Microprocessor Interface
5.1
Configuration interface
The CIMaX needs a clock source at 27MHz frequency with a duty cycle comprised between
33% and 67%. This frequency is commonly available in any digital video system.
A RESET input pin (active high) is available to reset the CIMaX at any time when power is on
(e.g. : power monitor, watchdog…). The clock must be activated before the end of the reset. The
reset signal must be active during at least 16 clock cycles (600ns @ 27MHz), before CIMaX
reset. The CIMaX is operational 8 cycles after reset deactivation.
CIMaX includes an input high order address bus A[25:15] to achieve address decoding for
automatic destination select or to be rerouted to the modules when using a memory PC Card
with HAD=1 and TSIEN=0 and TSOEN=0, in the Module Control Register.
The CIMaX configuration is achieved by accessing the various registers through a standard
I
2C interface. The I2C device address can be chosen among four values by connecting SA1 and
SA0 to VCC or GND. The binary address is 1 0 0 0 0 SA1 SA0 R/W. Though, the base address
can be chosen between 80h, 82h, 84h or 86h allowing the connection of up to four CIMaX on
the same bus.
Figure 5-1.
Chronograms
Parameter
Symbol
Min
Max
Unit
SCL frequency
f
SCL
400
KHz
Bus free time between stop and start
t
BUF
1.3
s
Hold time start condition
t
HD,STA
0.6
s
SCL low period
t
LOW
1.3
s
SCL high period
t
HIGH
0.6
s
SDA
SCL
t
BUF
t
HD,STA
t
LOW
t
R
t
HD,DAT
t
HIGH
t
F
t
SU,DAT
t
SU,STA
t
SU,STO
SDA
SCL
t
BUF
t
HD,STA
t
LOW
t
R
t
HD,DAT
t
HIGH
t
F
t
SU,DAT
t
SU,STA
t
SU,STO
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