參數(shù)資料
型號: T9000
廠商: Lineage Power
英文描述: ISDN Network Termination Node (NTN) Device(ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)器件)
中文描述: ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)(新界西)設(shè)備(ISDN網(wǎng)網(wǎng)絡(luò)終端節(jié)點(diǎn)器件)
文件頁數(shù): 70/126頁
文件大小: 1523K
代理商: T9000
70
Lucent Technologies Inc.
Advance Data Sheet
April 2000
ISDN Network Termination Node (NTN) Device
T9000
10 GCI+ Interface Module
(continued)
10.1 TDM Mode (GCCF, GMODE[1:0] = 1x)
(continued)
Table 78. TDM Data Rate and Clock Options
In TDM mode, the FSC signal can provide an envelope of time slot #0 (the first time slot of a frame) via the
GPIO2.2 pin by setting GPAF1[GPAF2.2] = 1. The PFS1 and PFS2 signals mark the location of the B1 and B2 time
slots on the TDM highway and are output on the FS1 and FS2 pins, respectively (see Table 78).
The PFS1 and PFS2 (programmable frame sync) signals may be programmed to be a pulse (duration of one bit
period, sometimes referred to as short frame sync) or envelope (duration of one time slot minus one-half of a DCL
period, sometimes referred to as long frame sync). Register bit GCCF[PFSPE] sets the short or long frame sync
mode.
The B1 and B2 time slots may be programmed to be at any offset from the start of the frame (in time-slot incre-
ments) by programming the GCOF1 and GCOF2 registers with the desired offset.
The U-interface B1 and B2 channels are normally transferred to/from the codec on the time slots marked by PFS1
and PFS2, respectively. This ordering can be switched by setting the DFAC[BSWAP] register bit to 1.
Register bit GCCF[PFSPE] = 1 controls the relative delay between PFSx (x = 1 or x = 2) and the first data bit of the
time slot associated with PFSx. When GCCF[PFSDEL] = 0, the PFSx rising edge is coincident with the start of the
first data bit of the corresponding time slot. When GCCF[PFSDEL] = 1, the PFSx rising edge occurs one data bit
prior to the first data bit of the corresponding time slot.
Generation of the PFSx signals and data transfer to/from the corresponding time slots may be disabled by setting
DFR[PFSx_ACT] = 0.
CKMODE
GRATE
DCL Rate (kHz)
BCLK Rate (kHz)
Data Rate (kHz)
Number of 8-bit
Time Slots
0
4
12
16
0
8
24
32
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
0
0
0
512
1536
2048
0
512
1536
2048
256
768
1024
0
0
0
0
256
768
1024
0
512
1536
2048
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