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參數(shù)資料
| 型號： | T9000 |
| 廠商： | Lineage Power |
| 英文描述： | ISDN Network Termination Node (NTN) Device(ISDN網(wǎng)絡終端節(jié)點器件) |
| 中文描述： | ISDN網(wǎng)絡終端節(jié)點（新界西）設備（ISDN網(wǎng)網(wǎng)絡終端節(jié)點器件） |
| 文件頁數(shù)： | 10/126頁 |
| 文件大?。?/td> | 1523K |
| 代理商： | T9000 |
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10
Lucent Technologies Inc.
Advance Data Sheet
April 2000
ISDN Network Termination Node (NTN) Device
T9000
4 Pin Information
(continued)
Table 4. GPIO Pins (24)
* I = input, O = output, I
d
= input with an internal 50 k
pull-down, I
U
= input with an internal 100 k
pull-up.
Pin Name
GPIO0.0
GPIO0.1
GPIO0.2
GPIO0.3
GPIO0.4 [PWMO00]
GPIO0.5 [PWMO01]
GPIO0.6 [PWMO10]
GPIO0.7 [PWMO11]
GPIO1.0
GPIO1.1
GPIO1.2
GPIO1.3
GPIO1.4 (USSP_E)
GPIO1.5 [T0]
GPIO1.6 [T1]
GPIO1.7 [T2]
Pin # Type*
72
73
74
75
76
77
78
79
81
82
83
84
85
86
87
88
Pin Description
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
d
/O
I
U
/O
I
U
/O
I
U
/O
General-Purpose Programmable I/O Port 0.
All of these pins may be con-
figured as inputs or outputs (see register GPDIR0). When programmed as
inputs, GPIO0.[3:0] may be configured as level or edge-triggered interrupt
sources for the 80C32 block (see register GPLEI). GPIO0.[3:0] have
Schmitt trigger input buffers. Internal 100 k
pull-up.
GPIO0.[7:6] and [5:4] may be alternatively configured (see register GPAF0)
as outputs from PWM modules 1 and 0, respectively.
General-Purpose Programmable I/O Port 1.
All of these pins may be con-
figured as inputs or outputs (see register GPDIR1). When programmed as
inputs, GPIO1.[3:0] may be configured as level- or edge-triggered interrupt
sources for the 80C32 block (see register GPLEI). GPIO1.[3:0] have
Schmitt trigger input buffers. Internal 100 k
pull-up.
GPIO1.[7:5] may be alternatively configured (see register GPAF1) as the
external trigger sources, T2, T1, and T0, respectively, for timers 2:0 on the
80C32 block.
U-Interface Send Single Pulses
—
Enable
. When the TEST pin is
asserted, this pin assumes the alternate function USSP_E. This function is
identical to that controlled by bit UCR1[USSP_E]. This input causes the
U-interface to continuously transmit single 2B1Q pulses on the U-interface.
The pulses occur at a rate of 1 pulse per 125
μ
s and alternate between pos-
itive and negative polarity. The magnitude of the pulses is controlled by bit
UCR1[USPMAG].
0: No effect on device operation.
1: U transmitter sends single pulses continuously.
General-Purpose Programmable I/O Port 2.
All of these pins may be con-
figured as inputs or outputs (see register GPDIR2). Internal 100 k
pull-up.
When programmed as an output, GPIO2.0 has a 6 mA current sinking
capability.
GPIO2.0
GPIO2.1 [BCLK]
GPIO2.2 [FSC]
GPIO2.3 [SYNCO]
GPIO2.4
GPIO2.5
GPIO2.6 [MTC]
GPIO2.7 (PTLB_S)
90
91
92
93
94
95
96
97
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
I
U
/O
GPIO2.6 becomes an input to the 8 kHz MTC signal when DOCR[NT-LT] bit
is set to 1 (register 0x50).
GPIO2.3 may be alternatively configured (see register GPAF1) as the dc/dc
output signal SYNCO (see Section 13.1, dc/dc Control Generator Register
Set).
GPIO2.2 may be alternatively configured (see register GPAF1) as the GCI+
signal FSC (see Section 10, GCI+ Interface Module).
GPIO2.1 may be alternatively configured (see register GPAF1) as the GCI+
signal BCLK (see Section 10, GCI+ Interface Module).
Pulse Template/Loopback, S-Interface
. When the TEST pin is asserted,
this pin assumes the alternate function PTLB_S. This input causes the
device to perform an S/T-only activation (equivalent to setting SCR0[STOA]
= 1), and enables a remote loopback towards the TE on the 2B+D channels
(equivalent to setting SCR1[RLB_D, RLB_B2, RLB_B1] = 1). This is useful
for performing pulse template and other tests on the S/T-interface. The U-
interface should be maintained inactive while this function is enabled.
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