參數(shù)資料
型號: T89C51CC02UA-TISIM
廠商: Atmel
文件頁數(shù): 91/159頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K 28SOIC
標(biāo)準(zhǔn)包裝: 27
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC02UATISIM
37
AT/T89C51CC02
4126L–CAN–01/08
Status of the Flash Memory
The bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
Selecting FM1
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.
Loading the Column Latches
Any number of data from 1 byte to 128 Bytes can be loaded in the column latches. This
provides the capability to program the whole memory by byte, by page or by any number
of Bytes in a page.
When programming is launched, an automatic erase of the locations loaded in the col-
umn latches is first performed, then programming is effectively done. Thus no page or
block erase is needed and only the loaded data are programmed in the corresponding
page.
The following procedure is used to load the column latches and is summarized in
Save then disable interrupt and map the column latch space by setting FPS bit.
Load the DPTR with the address to load.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
If needed loop the three last instructions until the page is completely loaded.
unmap the column latch and Restore Interrupt
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