參數(shù)資料
型號(hào): T89C51CC02UA-TISIM
廠商: Atmel
文件頁數(shù): 110/159頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K 28SOIC
標(biāo)準(zhǔn)包裝: 27
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC02UATISIM
54
AT/T89C51CC02
4126L–CAN–01/08
Registers
Table 33. SCON Register
SCON (S:98h)
Serial Control Register
Reset Value = 0000 0000b
bit addressable
7654
3210
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Description
7
FE
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SM0
Serial port Mode bit 0 (SMOD0 = 0)
Refer to SM1 for serial port mode selection.
6SM1
Serial port Mode bit 1
SM0 SM1
Mode
Baud Rate
0
Shift Register FXTAL/12 (or FXTAL/6 in mode X2)
0
1
8-bit UART
Variable
1
0
9bit UART
F
XTAL/64 or FXTAL/32
1
9bit UART
Variable
5SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter bit 8/Ninth bit to Transmit in Modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver bit 8/Ninth bit Received in Modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
1TI
Transmit Interrupt Flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
0RI
Receive Interrupt Flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, See Figure 22. and
Figure 23. in the other modes.
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