參數(shù)資料
型號： T89C51CC02UA-TISIM
廠商： Atmel
文件頁數(shù)： 7/159頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 16K 28SOIC
標(biāo)準(zhǔn)包裝： 27
系列： AT89C CAN
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
EEPROM 大小： 2K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
配用： AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱： T89C51CC02UATISIM
104
AT/T89C51CC02
4126L–CAN–01/08
Table 70. CANSTCH Register
CANSTCH (S:B2h) – CAN Message Object Status Register
Note:
No default value after reset.
765
43210
DLCW
TXOK
RXOK
BERR
SERR
CERR
FERR
AERR
Bit Number
Bit Mnemonic
Description
7DLCW
Data Length Code Warning
The incoming message does not have the DLC expected.
Whatever the frame type, the DLC field of the CANCONCH register
is updated by the received DLC.
6TXOK
Transmit OK
The communication enabled by transmission is completed.
When the controller is ready to send a frame, if two or more
message objects are enabled as producers, the lower index
message object (0 to 13) is supplied first. Must be cleared by
software.
This flag can generate an interrupt.
5RXOK
Receive OK
The communication enabled by reception is completed.
In the case of two or more message object reception hits, the lower
index message object (0 to 13) is updated first. Must be cleared by
software.
This flag can generate an interrupt.
4BERR
bit Error (only in transmission)
The bit value monitored is different from the bit value sent.
Exceptions:
the monitored recessive bit sent as a dominant bit during the
arbitration field and the acknowledge slot detecting a dominant bit
during the sending of an error frame. Must be cleared by software.
This flag can generate an interrupt.
3SERR
Stuff Error
Detection of more than five consecutive bits with the same polarity.
Must be cleared by software.
This flag can generate an interrupt.
2CERR
CRC Error
The receiver performs a CRC check on each destuffed received
message from the start of frame up to the data field.
If this checking does not match with the destuffed CRC field, a
CRC error is set. Must be cleared by software.
This flag can generate an interrupt.
1FERR
Form Error
The form error results from one or more violations of the fixed form
in the following bit fields:
CRC delimiter
acknowledgment delimiter
end_of_frame
Must be cleared by software.
This flag can generate an interrupt.
0AERR
Acknowledgment Error
No detection of the dominant bit in the acknowledge slot. Must be
cleared by software.
This flag can generate an interrupt.
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