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參數(shù)資料
| 型號： | T7690 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V T1/E1 Quad Line Interface(5.0 V T1/E1 四線接口) |
| 中文描述： | 5.0V的四線接口的T1/E1（5.0V的T1/E1的四線接口） |
| 文件頁數(shù)： | 30/42頁 |
| 文件大?。?/td> | 726K |
| 代理商： | T7690 |
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T7690 5.0 V T1/E1 Quad Line Interface
T7693 3.3 V T1/E1 Quad Line Interface
Data Sheet
May 1998
28
Lucent Technologies Inc.
Microprocessor Interface
(continued)
I/O Timing
The I/O timing specifications for the microprocessor interface are given in Table 21. The microprocessor interface
pins use CMOS I/O levels. All outputs, except the address/data bus AD[7:0], are rated for a capacitive load of
50 pF. The AD[7:0] outputs are rated for a 100 pF load. The minimum read and write cycle time is 200 ns for all
device configurations.
The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 5—12.
Table 21. Microprocessor Interface I/O Timing Specifications
Symbol
Configuration
Parameter
Setup
(ns)
(Min)
15
—
50
25
—
—
—
—
—
—
—
—
25
25
25
—
—
—
15
—
30
—
—
—
—
30
—
25
—
—
—
—
—
—
Hold
(ns)
(Min)
—
10
—
—
—
—
—
—
—
—
150
100
—
—
—
—
25
100
—
10
—
—
—
—
—
—
—
—
—
—
25
150
100
100
Delay
(ns)
(Max)
—
—
—
—
20
70
90
25
15
15
—
—
—
—
—
20
—
—
—
—
—
90
75
20
25
—
16
—
73
22
—
—
—
—
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
Modes 1 & 2
Address Valid to
AS
Asserted (Read, Write)
AS
Asserted to Address Invalid (Read, Write)
AS
Asserted to
DS
Asserted
R/
W
High (Read) to
DS
Asserted
DS
Asserted (Read, Write) to
DTACK
Asserted
DTACK
Asserted to Data Valid (Read)
DS
Asserted (Read) to Data Valid
DS
Negated (Read, Write) to
AS
Negated
DS
Negated (Read) to Data Invalid
DS
Negated (Read) to
DTACK
Negated
AS
(Read, Write) Asserted Width
DS
(Read) Asserted Width
AS
Asserted to R/
W
Low (Write)
R/
W
Low (Write) to
DS
Asserted
Data Valid to
DS
Negated (Write)
DS
Negated to
DTACK
Negated (Write)
DS
Negated to Data Invalid (Write)
DS
(Write) Asserted Width
Address Valid to ALE Asserted Low (Read, Write)
ALE Asserted Low (Read, Write) to Address Invalid
ALE Asserted Low to
RD
Asserted (Read)
RD
Asserted (Read) to Data Valid
RD
Asserted (Read) to RDY Asserted
RD
Negated to Data Invalid (Read)
RD
Negated to RDY Negated (Read)
ALE Asserted Low to
WR
Asserted (Write)
CS
Asserted to RDY Asserted Low
Data Valid to
WR
Negated (Write)
WR
Asserted (Write) to RDY Asserted
WR
Negated to RDY Negated (Write)
WR
Negated to Data Invalid
ALE Asserted (Read, Write) Width
RD
Asserted (Read) Width
WR
Asserted (Write) Width
Modes 3 & 4
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