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參數(shù)資料
| 型號(hào)： | T7690 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V T1/E1 Quad Line Interface(5.0 V T1/E1 四線接口) |
| 中文描述： | 5.0V的四線接口的T1/E1（5.0V的T1/E1的四線接口） |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 726K |
| 代理商： | T7690 |
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T7690 5.0 V T1/E1 Quad Line Interface
T7693 3.3 V T1/E1 Quad Line Interface
Data Sheet
May 1998
10
Lucent Technologies Inc.
Receiver
Data Recovery
The receive line interface transmission format of the
device is bipolar alternate mark inversion (AMI). It
accepts input data with a frequency tolerance of
±
130 ppm (DS1) or
±
80 ppm (CEPT). The receiver first
restores the incoming data and detects analog loss of
signal. Subsequent processing is optional and depends
on the programmable device configuration established
within the microprocessor interface registers. The
receiver operates with high interference immunity,
utilizing an equalizer to restore fast rise/fall times fol-
lowing maximum cable loss. The signal is then peak-
detected and sliced to produce digital representations
of the data.
Selectable clock recovery of the sliced data, digital loss
of signal, jitter attenuation, and data decoding are per-
formed. For applications bypassing the clock recovery
function (CDR = 0), the receive digital output format is
unretimed sliced data (RZ positive and negative data).
For clock recovery applications (CDR = 1), the receive
digital output format is nonreturn to zero (NRZ) with
selectable dual-rail or single-rail system interface. The
recovered clock (RCLK, pins 15, 37, 65, 87) is only pro-
vided when CDR = 1 (see Table 2).
Timing recovery is performed by a digital phase-locked
loop that uses XCLK (pin 29) as a reference to lock to
the incoming data. Because the reference clock is a
multiple of the received data rate, the output RCLK
(pins 15, 37, 65, 87) will always be a valid DS1/CEPT
clock that eliminates false-lock conditions. During peri-
ods with no input signal, the free-run frequency is
defined to be XCLK/16. RCLK is always active with a
duty-cycle centered at 50%, deviating by no more than
±
5%. Valid data is recovered within the first few bit peri-
ods after the application of XCLK. The delay of the data
through the receive circuitry is approximately 1 to 14 bit
periods, depending on the CDR and CODE configura-
tions. Additional delay is introduced if the jitter attenua-
tor is selected for operation in the receive path (see the
Data Delay section).
Jitter
The receiver is designed to accommodate large
amounts of input jitter. The receiver jitter performance
far exceeds the requirements shown in Table 4 and
Table 5. Jitter transfer is independent of input ones
density on the line interface.
Receiver Configuration Modes
Clock/Data Recovery Mode (CDR)
The clock/data recovery function in the receive path is
selectable via the CDR bit (register 5, bit 0). If CDR = 1,
the clock and data recovery function is enabled and
provides a recovered clock (RCLK) with retimed data
(RPD/RDATA, RND). If CDR = 0, the clock and data
recovery function is disabled, and the RZ data from the
slicers is provided over RPD and RND to the system. In
this mode, ALOS is available on the RCLK/ALOS pins,
and downstream functions selected by microprocessor
register 5 (JAR, ACM, LOSSD) are ignored.
Zero Substitution Decoding (CODE)
When single-rail operation is selected with DUAL = 0
(register 5, bit 4), the B8ZS/HDB3 zero substitution
decoding can be selected via the CODE bit (register 5,
bit 3). If CODE = 1, the B8ZS/HDB3 decoding function
is enabled in the receive path and decoded receive
data and code violations appear on the RDATA and
BPV pins, respectively. If CODE = 0, receive data and
any bipolar violations (such as two consecutive 1s of
the same polarity) appear on the RDATA and BPV pins,
respectively.
Alternate Logic Mode (ALM)
The alternate logic mode (ALM) control bit (register 5,
bit 5) selects the receive and transmit data polarity (i.e.,
active-high vs. active-low). If ALM = 0, the receiver cir-
cuitry (and transmit input) assumes the data to be
active-low polarity. If ALM = 1, the receiver circuitry
(and transmit input) assumes the data to be active-high
polarity. The ALM control is used in conjunction with the
ACM control (register 5, bit 6) to determine the receive
data retiming mode.
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