參數(shù)資料
型號(hào)： T7690
廠商： Lineage Power
英文描述： 5.0 V T1/E1 Quad Line Interface(5.0 V T1/E1 四線接口)
中文描述： 5.0V的四線接口的T1/E1（5.0V的T1/E1的四線接口）
文件頁數(shù)： 16/42頁
文件大?。?/td> 726K
代理商： T7690
T7690 5.0 V T1/E1 Quad Line Interface
T7693 3.3 V T1/E1 Quad Line Interface
Data Sheet
May 1998
14
Lucent Technologies Inc.
Transmitter
Output Pulse Generation
The transmitter accepts a clock with NRZ data in sin-
gle-rail mode (DUAL = 0: register 5, bit 4) or positive
and negative NRZ data in dual-rail mode (DUAL = 1)
from the system. The device converts this data to a bal-
anced bipolar signal (AMI format) with optional
B8ZS(DS1)/HDB3(CEPT) encoding and jitter attenua-
tion. Low-impedance output drivers produce these
pulses on the line interface. Positive 1s are output as a
positive pulse on TTIP, and negative 1s are output as a
positive pulse on TRING. Binary 0s are converted to
null pulses. The total delay of the data from the system
interface to the transmit driver is approximately 3 to 11
bit periods, depending on the CODE (register 5, bit 3)
configuration.
Additional delay results if the jitter attenuator is
selected for use in the transmit path (see the Data
Delay section).
Transmit pulse shaping is controlled by the on-chip
pulse-width controller and pulse equalizer. The pulse-
width controller produces the high-speed timing signals
to accurately control the transmit pulse widths. This
eliminates the need for a tightly controlled transmit
clock duty cycle that is usually required in discrete
implementations. The pulse equalizer controls the
amplitudes of these pulse shapes. Different pulse
equalizations are selected through proper settings of EQA, EQB, and EQC (registers 6 to 9, bits 5 to 7) as
described in Table 6.
Table 6. Equalizer/Rate Control
* In DS1 mode, the distance to the DSX for 22-gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types.
In CEPT mode, equalization is specified for coaxial or twisted-pair cable.
Loss measured at 772 kHz.
In 75
applications, option 1 is recommended over option 2 for lower device power dissipation. Option 2 allows for the same transformer as
used in CEPT 120
applications.
Jitter
The intrinsic jitter of the transmit path, i.e., the jitter at TTIP/TRING when no jitter is applied to TCLK (and the jitter
attenuator is not selected, JAT = 0), is typically 5 ns
pk-pk
and will not exceed 0.02 UI
pk-pk
.
EQA
EQB
EQC
Service
Clock
Rate
Transmitter Equalization
*
Maximum
Cable
Loss
Feet
Meters
0 m to 40 m
40 m to 80 m
80 m to 120 m
120 m to 160 m
160 m to 200 m
dB
0.6
1.2
1.8
2.4
3.0
—
—
—
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DS1
1.544 MHz
0 ft. to 131 ft.
131 ft. to 262 ft.
262 ft. to 393 ft.
393 ft. to 524 ft.
524 ft. to 655 ft.
CEPT
2.048 MHz
75
(Option 2)
120
or 75
(Option 1)
—
Not Used
—
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