參數(shù)資料
型號(hào)： T7689
廠商： Lineage Power
英文描述： 5.0 V T1 Quad Line Interface(5.0 V T1四線接口)
中文描述： 5.0V的T1四線接口（5.0V的T1四線接口）
文件頁(yè)數(shù)： 8/38頁(yè)
文件大?。?/td> 548K
代理商： T7689
Data Sheet
May 1998
T7689 5.0 V T1 Quad Line Interface
8
Lucent Technologies Inc.
25
INT
O
Interrupt
. This pin is asserted high to indicate an interrupt produced by an
alarm condition in register 0 or 1. The activation of this pin can be masked
by microprocessor registers 2, 3, and 4.
26
RDY_DTACK
O
Ready
. If MPMODE = 1 (pin 21), this pin is asserted high to indicate the
device has completed a read or write operation. This pin is in a 3-state con-
dition when CS (pin 24) is high.
Data Transfer Acknowledge (Active-Low).
If MPMODE = 0 (pin 21), this
pin is asserted low to indicate the device has completed a read or write
operation.
27, 78
GND
C
P
Ground Reference for Microprocessor Interface and Control Circuitry
.
28, 77
V
DDC
P
Power Supply for Microprocessor Interface and Control Circuitry.
The
T7689 device requires a 5 V
±
5% power supply on these pins.
Reference Clock
. A valid reference clock (24.704 MHz
±
100 ppm for DS1
operation) must be provided at this input for certain applications (see the
XCLK Reference Clock section). XCLK must be an independent, continu-
ously active, ungapped, and unjittered clock to guarantee device perfor-
mance specifications. An internal 100 k
pull-up is on this pin.
Blue Clock
. Input clock signal used to transmit the blue signal (all 1s data
pattern). In DS1 mode, this clock is 1.544 MHz
±
32 ppm. An internal
100 k
pull-up is on this pin.
Loss of XCLK
.
This pin is asserted high when the XCLK signal (pin 29) is
not present.
29
XCLK
I
u
30
BCLK
I
u
31
LOXC
O
32
RESET
I
u
Hardware Reset (Active-Low)
. If
RESET
is forced low, all internal states in
the line interface paths are reset and data flow through each channel will be
momentarily disrupted (see the RESET (
RESET
, SWRESET) section). The
RESET
pin must be held low for a minimum of 10
μ
s. An internal 50 k
pull-
up is on this pin.
33
ICT
I
u
In-Circuit Test Control (Active-Low)
. If
ICT
is forced low, certain output
pins are placed in a high-impedance state (see the In-Circuit Testing and
Driver 3-State (ICT) section). An internal 50 k
pull-up is on this pin.
Microprocessor Interface Address/Data Bus.
If MPMUX = 0 (pin 20),
these pins become the bidirectional, 3-statable data bus. If MPMUX = 1,
these pins become the multiplexed address/data bus. In this mode, only the
lower 4 bits (AD[3:0]) are used for the internal register addresses.
69
AD7
I/O
70
AD6
71
AD5
72
AD4
73
AD3
74
AD2
75
AD1
76
AD0
Table 1. Pin Descriptions
(continued)
Pin
Symbol
Type
*
Name/Description
* P = power, I = input, O = output, and I
u
= input with internal pull-up.
Pin Information
(continued)
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