- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T7689 (Lineage Power) 5.0 V T1 Quad Line Interface(5.0 V T1四線接口) PDF資料下載
參數(shù)資料
| 型號： | T7689 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V T1 Quad Line Interface(5.0 V T1四線接口) |
| 中文描述： | 5.0V的T1四線接口（5.0V的T1四線接口） |
| 文件頁數(shù)： | 34/38頁 |
| 文件大?。?/td> | 548K |
| 代理商： | T7689 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁
Data Sheet
May 1998
T7689 5.0 V T1 Quad Line Interface
34
Lucent Technologies Inc.
Operating Conditions
(continued)
* A single channel (receive and transmit paths) for 50% ones density data.
For standby purposes. If a channel will never be used, connecting all V
DD
pins to the ground plane is recommended, resulting in no power
consumption.
For nominal V
DD
, T
A
= 25
°
C. Every function and channel operational with 50% ones density.
§ For V
DD
= 5.25 V and T
A
= 25
°
C. Every function and channel operational with 100% ones density.
Timing Characteristics
* 100 pF allowed for AD[7:0] (pins 69 to 76).
Table 26. Power Specifications (V
DD
= 5 V and T
A
= 25
°
C; Device power specification includes power to the
line for a specified data ones density.)
Parameter
T7689
Unit
Per Channel*: (typical)
CDR = 0, JAx = 0 (transmit, receiver in data slicing
mode, no jitter attenuator)
CDR = 1, JAx = 0 (transmit, receiver in clock recovery
mode, no jitter attenuator)
CDR = 1, JAx = 1 (transmit, receiver in clock recovery
mode, jitter attenuator active)
During Powerdown Mode (PWRDN = 1)
Quad Total:
Typical
Max
83
97
100
2.5
mW
mW
mW
mW
412
780
§
mW
mW
Table 27. Logic Interface Characteristics
An internal 50 k
pull-up is provided on the
ICT
and
RESET
pins. An internal 100 k
pull-up is provided on the
CS
,
XCLK, and BCLK pins. This requires these input pins to sink no more than 20
μ
A. All buffers use CMOS levels.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Voltage:
Low
High
Input Leakage
Output Voltage:
Low
High
Input Capacitance
Load Capacitance*
V
IL
V
IH
I
L
—
—
—
GND
D
V
DDD
– 1.0
—
1.0
V
DDD
1.0
V
V
μ
A
V
OL
V
OH
C
I
C
L
–5.0 mA
5.0 mA
—
—
GND
D
V
DDD
– 1.0
—
—
0.5
V
DDD
3.0
50
V
V
pF
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7690 | 5.0 V T1/E1 Quad Line Interface(5.0 V T1/E1 四線接口) |
| T7693 | 3.3 V T1/E1 Quad Line Interface( 3.3 V T1/E四線接口) |
| T7698 | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| T7705A | SUPPLY-VOLTAGE SUPERVISORS |
| T8100A | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)間段交換機(jī)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T-7689-FL | 制造商:Alcatel-Lucent 功能描述:DATACOM, PCM TRANSCEIVER, 100 Pin Plastic QFP |
| T-7689---FL-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:LSI Corporation 功能描述: |
| T-7690-FL | 制造商:Alcatel-Lucent 功能描述:PCM TRANSCEIVER, Quad, CEPT PCM-30/E-1, 100 Pin, Plastic, QFP |
| T77 | 制造商:Thomas & Betts 功能描述:2-1/2"CONDUIT BODY,IRON,T,F-7 制造商:Cooper Crouse-Hinds 功能描述: 制造商:Thomas & Betts 功能描述:Fittings T-Fitting 2.5inch Non-Thread Iron |
| T7700 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Core2 Duo Processors and Core2 Extreme Processors for Platforms Based on Mobile 965 Express Chipset Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。