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參數(shù)資料
| 型號： | T7689 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V T1 Quad Line Interface(5.0 V T1四線接口) |
| 中文描述： | 5.0V的T1四線接口（5.0V的T1四線接口） |
| 文件頁數(shù)： | 23/38頁 |
| 文件大?。?/td> | 548K |
| 代理商： | T7689 |
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Data Sheet
May 1998
T7689 5.0 V T1 Quad Line Interface
23
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Interface Register Architecture
(continued)
Alarm Register Overview (0000, 0001)
The bits in the alarm registers represent the status of the transmitter and receiver alarms LOTC, TDM, DLOS, and
ALOS for all four channels as shown in Table 14. The alarm indicators are active-high and automatically clear on a
microprocessor read if the corresponding alarm condition no longer exists. Persistent alarm conditions will cause
the bit to remain set. These are read-only registers.
* The numerical suffix identifies the channel number.
Alarm Mask Register Overview (0010, 0011)
The bits in the alarm mask registers in Table 15 allow the microprocessor to selectively mask each channel alarm
and prevent it from generating an interrupt. The mask bits correspond to the alarm status bits in the alarm registers
and are active-high to disable the corresponding alarm from generating an interrupt. These registers are read/write
registers.
* The numerical suffix identifies the channel number.
Table 14. Alarm Registers
Bits
Symbol
*
Description
Alarm Register (0)
Analog loss of signal alarm for channels 1 & 2.
Digital loss of signal alarm for channels 1 & 2.
Transmit driver monitor alarm for channels 1 & 2.
Loss of transmit clock alarm for channels 1 & 2.
Alarm Register (1)
Analog loss of signal alarm for channels 3 & 4.
Digital loss of signal alarm for channels 3 & 4.
Transmit driver monitor alarm for channels 3 & 4.
Loss of transmit clock alarm for channels 3 & 4.
0, 4
1, 5
2, 6
3, 7
ALOS[1:2]
DLOS[1:2]
TDM[1:2]
LOTC[1:2]
0, 4
1, 5
2, 6
3, 7
ALOS[3:4]
DLOS[3:4]
TDM[3:4]
LOTC[3:4]
Table 15. Alarm Mask Registers
Bits
Symbol
*
Description
Alarm Mask Register (2)
Mask analog loss of signal alarm for channels 1 & 2.
Mask digital loss of signal alarm for channels 1 & 2.
Mask transmit driver monitor alarm for channels 1 & 2.
Mask loss of transmit clock alarm for channels 1 & 2.
Alarm Mask Register (3)
Mask analog loss of signal alarm for channels 3 & 4.
Mask digital loss of signal alarm for channels 3 & 4.
Mask transmit driver monitor alarm for channels 3 & 4.
Mask loss of transmit clock alarm for channels 3 & 4.
0, 4
1, 5
2, 6
3, 7
MALOS[1:2]
MDLOS[1:2]
MTDM[1:2]
MLOTC[1:2]
0, 4
1, 5
2, 6
3, 7
MALOS[3:4]
MDLOS[3:4]
MTDM[3:4]
MLOTC[3:4]
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