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參數(shù)資料
| 型號： | T7688 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口) |
| 中文描述： | 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口） |
| 文件頁數(shù)： | 9/38頁 |
| 文件大?。?/td> | 577K |
| 代理商： | T7688 |
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Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
9
Lucent Technologies Inc.
System Interface Pin Options
The system interface can be configured to operate in a number of different modes, as shown in Table 2. Dual-rail or
single-rail operation is possible using the DUAL control bit (register 5, bit 4). Dual-rail mode is enabled when
DUAL = 1; single-rail mode is enabled when DUAL = 0. In dual-rail operation, data received from the line interface
on RTIP and RRING appears on RPD (pins 14, 38, 64, 88) and RND (pins 13, 39, 63, 89) at the system interface
and data transmitted from the system interface on TPD (pins 17, 35, 67, 85) and TND (pins 16, 36, 66, 86) appears
on TTIP and TRING at the line interface. In single-rail operation, data received from the line interface on RTIP and
RRING appears on RDATA (pins 14, 38, 64, 88) at the system interface and data transmitted from the system inter-
face on TDATA (pins 17, 35, 67, 85) appears on TTIP and TRING at the line interface.
In both dual-rail and single-rail operation, the clock/data recovery mode is selectable via the CDR bit (register 5,
bit 0). When CDR = 1, the clock and data recovery is enabled and the system interface operates in a nonreturn to
zero (NRZ) digital format. When CDR = 0, the clock and data recovery is disabled and the system interface oper-
ates on unretimed sliced data in RZ data format (see the Data Recovery section).
In single-rail mode only, HDB3 encoding/decoding may be selected by setting CODE = 1 (register 5, bit 3). This
allows coding violations, such as receiving two consecutive 1s of the same polarity from the line interface, to be
output on BPV (pins 13, 39, 63, 89) (see the Zero Substitution Encoding/Decoding (CODE) section).
79
A3
I
Microprocessor Interface Address.
If MPMUX = 0 (pin 20), these pins
become the address bus for the microprocessor interface registers. If
MPMUX = 1, A3 (pin 79) can be externally tied high to use the internal chip
selection function (see the Internal Chip Select Function section). If this
function is not used, A[3:0] must be externally tied low.
80
A2
81
A1
82
A0
83
MPCLK
I
Microprocessor Interface Clock.
Microprocessor interface clock rates
from twice the frequency of the line clock (4.096 MHz for CEPT operation) to
16.384 MHz are supported.
Table 2. Pin Mapping
Configuration
RCLK/
ALOS
RCLK
ALOS
RCLK
ALOS
RPD/
RDATA
RPD
RPD
RDATA
RPD
RND/BPV
TPD/
TDATA
TND
Dual-rail System Interface with Clock Recovery
Dual-rail System Interface with Data Slicing Only
Single-rail System Interface with Clock Recovery
Single-rail System Interface with Data Slicing Only
RND
RND
BPV
RND
TPD
TND
TDATA
NOT
USED
Table 1. Pin Descriptions
(continued)
Pin
Symbol
Type
*
Name/Description
* P = power, I = input, O = output, and I
u
= input with internal pull-up.
Pin Information
(continued)
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