參數(shù)資料
型號(hào)： T7688
廠商： Lineage Power
英文描述： 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口)
中文描述： 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口）
文件頁(yè)數(shù)： 35/38頁(yè)
文件大?。?/td> 577K
代理商： T7688
Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
35
Lucent Technologies Inc.
Timing Characteristics
(continued)
* Refers to each individual bit period for JAT = 0 applications.
Refers to each individual bit period for JAT = 1 applications using a gapped TCLK.
5-1156(C)r.8
* Invert RCLK for ACM = 1.
Figure 13. Interface Data Timing (ACM = 0)
Table 26. Interface Data Timing
The digital system interface timing is shown in Figure 13 for ACM = 0. If ACM = 1, then the RCLK signal in
Figure 13 will be inverted.
Symbol
tTCLTCL
Parameter
Min
Typ
Max
Unit
Average TCLK Clock Period:
CEPT
TCLK Duty Cycle*
TCLK Minimum High/Low Time
Transmit Data Setup Time
Transmit Data Hold Time
Clock Rise Time (10%/90%)
Clock Fall Time (90%/10%)
RCLK Duty Cycle
Receive Data Setup Time
Receive Data Hold Time
Receive Propagation Delay
—
30
100
50
40
—
—
45
140
180
—
488.0
—
—
—
—
—
—
50
—
—
—
—
70
—
—
—
40
40
55
—
—
40
ns
%
ns
ns
ns
ns
ns
%
ns
ns
ns
tTDC
tTDVTCL
tTCLTDX
tTCH1TCH2
tTCL2TCL1
tRCHRCL
tRDVRCH
tRCHRDX
tRCLRDV
TCLK
TPDATA
OR
TNDATA
RCLK*
RPDATA
OR
RNDATA
tTCLTCL
tTCH1TCH2
tTCL2TCL1
tTDVTCL
tTCLTDX
tRCLRDV
tRDVRCH
tRCHRDX
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