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參數(shù)資料
| 型號： | T7688 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口) |
| 中文描述： | 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口） |
| 文件頁數(shù)： | 11/38頁 |
| 文件大小： | 577K |
| 代理商： | T7688 |
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Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
11
Lucent Technologies Inc.
Receiver
(continued)
Receiver Configuration Modes
(continued)
Alternate Clock Mode (ACM)
The alternate clock mode (ACM) control bit (register 5,
bit 6) selects the positive or negative clock edge of the
receive clock (RCLK) for receive data retiming. The
ACM control is used in conjunction with ALM (register
5, bit 5) control to determine the receive data retiming
modes. If ACM = 1, the receive data is retimed on the
positive edge of the receive clock. If ACM = 0, the
receive data is retimed on the negative edge of the
receive clock. Note that this control does not affect the
timing relationship for the transmitter inputs.
Loss Shut Down (LOSSD)
The loss shut down (LOSSD) control bit (register 5,
bit 7) places the digital receiver outputs (RPD, RND) in
a predetermined state when a digital loss of signal
(DLOS) alarm occurs in register 0 and 1, bits 1 and 5. If
LOSSD = 1, the RPD and RND outputs are forced to
their inactive states (selected by ALM) and the receive
clock (RCLK) free runs during a DLOS alarm condition.
If LOSSD = 0, the RPD, RND, and RCLK outputs will
remain unaffected during the DLOS alarm condition.
Receiver Alarms
Analog Loss of Signal (ALOS) Alarm
An analog loss of signal (ALOS) detector monitors the
incoming signal amplitude and reports its status to
the alarm registers 0 and 1. During CEPT mode of
operation, analog loss of signal is indicated (ALOS = 1)
if the amplitude at the receive input drops below a volt-
age that is 17 dB below the nominal pulse amplitude.
The slicer outputs are clamped to the inactive state,
and the clock recovery will provide a free-running
RCLK when ALOS = 1. The alarm circuitry also pro-
vides 4 dB of hysteresis to eliminate ALOS chattering.
The time required to detect ALOS is between 1 ms and
2.6 ms and is timed by the blue clock (see the All Ones
(AIS, Blue Signal) Generator (TBS) section). Detection
time is independent of signal amplitude before the loss
condition occurs.
Digital Loss of Signal (DLOS) Alarm
A digital loss of signal (DLOS) detector guarantees the
quality of the signal as defined in standards documents
G.775, and reports its status to the alarm registers 0
and 1. During CEPT operation, DLOS is indicated
when 255 or more consecutive 0s occur in the receive
data stream. The DLOS indication is deactivated when
the average ones density of at least 12.5% is received
in 255 contiguous pulse positions.
Bipolar Violation (BPV) Alarm
The bipolar violation (BPV) alarm is used only in single-
rail mode of operation of the device (see the System
Interface Pin Options section). When HDB3(CEPT)
coding is not used (i.e., CODE = 0), any violations in
the receive data (such as two or more consecutive 1s
on a rail) are indicated on the RND/BPV pins. When
HDB3(CEPT) coding is used (i.e., CODE = 1), the
HDB3 code violations are reflected on the RND/BPV
pins.
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