參數(shù)資料
型號(hào)： T7688
廠商： Lineage Power
英文描述： 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口)
中文描述： 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口）
文件頁(yè)數(shù)： 18/38頁(yè)
文件大?。?/td> 577K
代理商： T7688
Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
18
Lucent Technologies Inc.
Other Features
Powerdown (PWRDN)
Each line interface channel has an independent power-
down mode controlled by PWRDN (registers 6 to 9,
bit 0). This provides power savings for systems that use
backup channels. If PWRDN = 1, the corresponding
channel will be in a standby mode, consuming only a
small amount of power. It is recommended that the
alarm registers for the corresponding channel be
masked with MASK = 1 (registers 6 to 9, bit 1) during
powerdown mode. If a line interface channel in power-
down mode needs to be placed into service, the chan-
nel should be turned on (PWRDN = 0) approximately
5 ms before data is applied.
If a line interface channel will never be in service, the
V
DDA
and V
DDD
pins can be connected to the ground
plane, resulting in no power consumption.
RESET (
RESET
, SWRESET)
The device provides both a hardware reset (
RESET
;
pin 32) and a software reset (SWRESET; register 4,
bit 1) that are functionally equivalent. When the device
is in reset, all signal-path and alarm monitor states are
initialized to a known starting configuration. The status
registers and INT (pin 25) are also cleared. The writ-
able microprocessor interface registers are not affected
by reset, with the exception of bits in register 4 (see the
Global Control Register Overview (0100, 0101) sec-
tion). During a reset condition, data transmission will be
momentarily interrupted and the device will respond to
those register bits affected by the reset. On powerup of
the device, the software reset bit (register 4, bit 1) is not
initialized. It must be written to a zero prior to writing
the other bits in register 4.
The reset condition is initiated by setting
RESET
= 0 or
SWRESET = 1 for a minimum of 10
μ
s. After leaving
the reset condition (with
RESET
= 1 or SWRESET = 0),
only the bits in register 4 need to be restored.
Loss of XCLK Reference Clock (LOXC)
The LOXC output (pin 31) is active when the XCLK ref-
erence clock (pin 29) is absent. The LOXC flag is
asserted between 150 ns and 700 ns after XCLK dis-
appears, and deasserts immediately after detecting the
first clock edge of XCLK.
During the LOXC alarm condition, the clock recovery
and jitter attenuator functions are automatically dis-
abled. Therefore, if CDR = 1 and/or JAR = 1, the RCLK,
RPD, RND, and DLOS outputs will be unknown. If
CDR = 0, there will be no effect on the receiver. If the
jitter attenuator is enabled in the transmit path (JAT = 1)
during this alarm condition, then LOTC = 1 will also be
indicated.
In-Circuit Testing and Driver 3-State (
ICT
)
The function of the
ICT
input (pin 33) is determined by
the ICTMODE bit (register 4, bit 3). If ICTMODE = 0
and
ICT
is activated (
ICT
= 0), then all output buffers
(TTIP, TRING, RCLK, RPD, RND, LOXC, RDY_
DTACK
,
INT, AD[7:0]) are placed in a high-impedance state. For
in-circuit testing, the
RESET
pin can be used to activate
ICTMODE = 0 without having to write the bit. If ICT-
MODE = 1 and
ICT
= 0, then only the TTIP and TRING
outputs of all channels will be placed in a high-
impedance state. The TTIP and TRING outputs have a
limiting high-impedance capability of approximately
8 k
.
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