參數(shù)資料
型號(hào)： T7688
廠商： Lineage Power
英文描述： 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口)
中文描述： 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口）
文件頁(yè)數(shù)： 19/38頁(yè)
文件大?。?/td> 577K
代理商： T7688
Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
19
Lucent Technologies Inc.
Microprocessor Interface
Overview
The device is equipped with a microprocessor interface
that can operate with most commercially available
microprocessors. Inputs MPMUX and MPMODE
(pins 20 and 21) are used to configure this interface
into one of four possible modes, as shown in Table 8.
The MPMUX setting selects either a multiplexed 8-bit
address/data bus (AD[7:0]) or a demultiplexed 4-bit
address bus (A[3:0]) and an 8-bit data bus (AD[7:0]).
The MPMODE setting selects the associated set of
control signals required to access a set of registers
within the device.
When the microprocessor interface is configured to
operate in the multiplexed address/data bus modes
(MPMUX = 1), the user has access to an internal chip
select function that allows the microprocessor to selec-
tively read/write a specific T7688 in a multiple T7688
environment (see the Internal Chip Select Function
section).
The microprocessor interface can operate at speeds up
to 16.384 MHz in interrupt-driven or polled mode with-
out requiring any wait-states. For microprocessors
operating at greater than 16.384 MHz, the
RDY_DTACK output is used to introduce wait-states in
the read/write cycles.
In the interrupt-driven mode, one or more device
alarms will assert the active-high INT output (pin 25)
once per alarm activation. After the microprocessor
reads the alarm status registers, the INT output will
deassert. In the polled mode, however, the micropro-
cessor monitors the various device alarm status by
periodically reading the alarm status registers without
the use of INT (pin 25). In both interrupt and polled
methods of alarm servicing, the status register will
clear on a microprocessor read cycle only when the
alarm condition within the signaling channel no longer
exists; otherwise, the register bit remains set.
Due to the device flexibility, there are no default power-
up or reset states, except for register 4. All read/write
registers must be written by the microprocessor on sys-
tem start-up to guarantee proper device functionality.
Details concerning microprocessor interface configura-
tion modes, pinout definitions, clock specifications,
register bank architecture, and the I/O timing specifica-
tions and diagrams are described in the following sec-
tions.
Microprocessor Configuration Modes
Table 8 highlights the four microprocessor modes con-
trolled by the MPMUX and MPMODE inputs (pins 20
and 21).
Table 8. Microprocessor Configuration Modes
Mode
MPMODE
MPMUX
Address/Data Bus
Generic Control, Data, and
Output Pin Names
CS
,
AS
,
DS
, R/
W
, A[3:0], AD[7:0], INT,
DTACK
CS
,
AS
,
DS
, R
/W
, AD[7:0], INT,
DTACK
CS
, ALE,
RD
,
WR
, A[3:0], AD[7:0], INT, RDY
CS
, ALE,
RD
,
WR
, AD[7:0], INT, RDY
MODE1
MODE2
MODE3
MODE4
0
0
1
1
0
1
0
1
DEMUXed
MUXed
DEMUXed
MUXed
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