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參數(shù)資料
| 型號： | T7536 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組) |
| 中文描述： | 16通道可編程解碼器芯片組（十六通道可編程編解碼器芯片組） |
| 文件頁數(shù)： | 9/44頁 |
| 文件大小： | 772K |
| 代理商： | T7536 |
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Lucent Technologies Inc.
9
Data Sheet
February 1999
Codec Chip Set
T7531A/T7536 16-Channel Programmable
Pin Information
(continued)
Table 1. T7536 Pin Descriptions
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; I
d
indicates a pull-down
device is included on this lead, I
u
indicates a pull-up device is included on this lead.
Number
9, 17, 19, 27,
43, 51, 53, 61
10, 16, 20, 26,
44, 50, 54, 60
11, 15, 21, 25,
45, 49, 55, 59
12, 14, 22, 24,
46, 48, 56, 58
8, 18, 28, 38,
42, 52, 62
Name
VTX[7:0]
Type
AI
Name/Function
Analog Input.
Transmit signal voltage to be encoded.
VRTX[7:0]
AI
Transmit Reference Voltage.
+2.4 V reference. Each pin must have a
separate supply associated with the corresponding VTX pin.
Noninverting Receive Output.
This pin can drive high-impedance loads
either differentially or single ended. It is the complement of the VRN output.
Inverting Receive Output.
This pin can drive high-impedance loads either
differentially or single ended. It is the complement of the VRP output.
+5 V Analog Power Supply.
Power supply decoupling capacitor (0.1
μ
F)
should be connected from each V
DDA
pin to analog ground. Capacitors
should be located as close as possible to the device pins.
Analog Ground.
VRP[7:0]
AO
VRN[7:0]
AO
V
DDA
—
13, 23, 31,
47, 57
63
V
SSA
—
V
DDD
—
+5 V Digital Power Supply.
Decouple with a 0.1
μ
F capacitor to digital
ground.
Digital Ground.
Oversampled Transmit Data.
Four channels of 1.024 MHz
Σ
-
transmit
data is transmitted to the T7531A through each of these pins. The data rate
is 4.096 MHz.
Oversampled Receive Data.
Four channels of 1.024 MHz
Σ
-
receive
data is received from the T7531A on each of these pins. The data rate is
4.096 MHz.
Interface Clock.
The 4.096 MHz clock that enters this pin from the T7531A
serves as the bit clock for all the oversampled data transmission between
this chip and the T7531A. This is the master clock input for the T7536.
Interface Frame Sync.
This signal serves as the frame sync for the over-
sampled data interface between the T7536 and the T7531A.
Control Data Interface Input.
The T7531A sends control register address
and data to the T7536 through this pin. One address byte and one data
byte are accepted each time CCS is toggled.
Control Data Interface Output.
Control register contents are clocked out
through this pin.
Control Interface Chip Select (Active-Low).
This active-low input
enables the control interface.
Reset (Active-Low).
This input must be pulled high for normal operation.
When pulled momentarily low (at least 1
μ
s) while OSCK is active, all pro-
grammable registers in the device are reset to the states specified under
powerup initialization. This pin has an internal pull-up resistor.
Test.
This pin is for factory test purposes only. Connect to V
DDD
for normal
operation. This pin has an internal pull-down resistor.
No Connect.
No connection to chip. These pins can be used as logic level
tie points.
7
V
SSD
—
CO
5, 4
OSDX[1:0]
6, 3
OSDR[1:0]
CI
2
OSCK
CI
1
OSFS
CI
66
CDI
CI
64
CDO
CO
65
CCS
CI
68
RSTB
TI
u
67
TEST
TI
d
29, 30, 32—37,
39—41
NC
—
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