- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T7536 (Lineage Power) 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組) PDF資料下載
參數(shù)資料
| 型號： | T7536 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組) |
| 中文描述： | 16通道可編程解碼器芯片組（十六通道可編程編解碼器芯片組） |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 772K |
| 代理商： | T7536 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
16
Lucent Technologies Inc.
Data Sheet
February 1999
Codec Chip Set
T7531A/T7536 16-Channel Programmable
Chip Set Functional Description
(continued)
T7531A Functional Blocks
(continued)
Addresses
≥
0x1400 refer to registers or TSA RAM
external to the DSP engine. If the address word from
the microprocessor is 0x1400 through 0x140F, it acti-
vates the TSA state machine. If the address word from
the microprocessor is 0x1500 through 0x15FF, it acti-
vates the T7536 control state machine.
Microprocessor data and address words can be
flushed out of the T7531A by addressing 0x7FFF with
data word 0xFFFF (see Table 40).
T7536 Octal Control Interface
The two T7536 chips cannot be accessed by the micro-
controller directly; the T7536's registers are all
accessed via the T7531A microprocessor interface.
The microprocessor communicates serially with the
T7536 by simply writing or reading 16-bit address and
16-bit data. The octal control interface block translates
this address and data into 8-bit address and 8-bit data
needed by the T7536. The octal control interface block
waits until the microprocessor interface block receives
all 16 bits of the address word and determines whether
this is a read or write operation by looking at bit 15. If
this is a write operation for a T7536 chip, it receives
another 16-bit data word.
T7531A Time-Slot Assignment (TSA)
The TSA block contains a 16 x 6 dual-port RAM which
is readable or writable via the microprocessor interface.
Table 18 gives the bit map for TSA RAM words. The
TSA RAM is in time-slot order, i.e., location 0x1400 is
for time slot 0 and 0x1401 for time slot 1 and so on. The
low 4 bits (B3—B0) indicate which of the 16 possible
channel numbers is assigned to this time slot. The
time-slot assignment is controlled by the microproces-
sor writing to address 0x1400 through 0x140F.
The TSA block also generates the control signals and
flags used to synchronize the TSA, interpolator and
decimator, and T7536 interface blocks. The TSA RAM
is not preinitialized, so the microprocessor is required
to write to all 16 locations of the TSA RAM at start-up
to ensure proper operation. Twice a frame, the TSA
state machine reads the entire TSA RAM from top to
bottom in sequence and sends the contents of each
RAM location to the interpolator as channel numbers
for RX channels. The TSA state machine performs the
same procedure for the decimator to provide it with the
TX channel numbers. By performing TSA at the over-
sampled sigma-delta rate, round trip group delay is sig-
nificantly minimized.
DSP Engine Timing
The DSP engine processes all 16 lines every frame. In
order to simplify synchronization of data exchanges,
the processing frame is broken into 16 equal time seg-
ments of 7.8
μ
s each. The ROM code is identical for
each time segment.
Synchronization between the engine and the rest of the
chip is enforced by the system interface block, which
issues an interrupt every 7.8
μ
s. This interrupt is the
only unmasked interrupt processed by the engine. The
interrupt service routine forces the ROM code to
branch to the start of the processing loop.
T7531A Program Structure
The DSP engine firmware performs three types of
operations:
1.Signal processing of the ac path data.
2.RAM accesses initiated by the microprocessor
interface.
3.Data and program flow operations.
The signal processing algorithms performed by the
T7531A are implemented in firmware and are held in
ROM.
Many firmware parameters are user programmable via
the microprocessor interface. Interrupts from the micro-
processor interface are handled once every time seg-
ment (7.8
μ
s), and the appropriate accesses are made
to the DSP engine RAM registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7531A | 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組) |
| T7570 | Programmable PCM Codec with Hybrid-Balance Filter(帶混合平衡濾波器的可編程PCM編解碼器) |
| T7633 | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| T7688 | 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口) |
| T7689 | 5.0 V T1 Quad Line Interface(5.0 V T1四線接口) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7570 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T7570 Programmable PCM Codec with Hybrid-Balance Filter |
| T-758 | 制造商:RHOMBUS-IND 制造商全稱:Rhombus Industries Inc. 功能描述:Transformer |
| T-759 | 制造商:RHOMBUS-IND 制造商全稱:Rhombus Industries Inc. 功能描述:SCHEMATIC DIAGRAM |
| T75A | 制造商:EGS Appleton 功能描述:Exact Equal/ 1-5 Days |
| T75F-C | 功能描述:非熱縮管和套管 SPIRAL WRAP 3/4 100’ RoHS:否 制造商:Panduit 產(chǎn)品:Cable Wraps 類型:Spiral 顏色:Black 材料:PP 內(nèi)徑:0.03 in 長度:100 ft |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。