參數(shù)資料
型號(hào)： T7536
廠商： Lineage Power
元件分類： Codec
英文描述： 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組)
中文描述： 16通道可編程解碼器芯片組（十六通道可編程編解碼器芯片組）
文件頁(yè)數(shù)： 14/44頁(yè)
文件大?。?/td> 772K
代理商： T7536
14
Lucent Technologies Inc.
Data Sheet
February 1999
Codec Chip Set
T7531A/T7536 16-Channel Programmable
Chip Set Functional Description
(continued)
Other Chip Set Functions
(continued)
Digital Termination Impedance Synthesis
The CTZ filter in the T7531A synthesizes complex ter-
mination impedances. The CTZ filter utilizes alpha and
beta coefficients (board control words 4 and 5, respec-
tively) to perform the synthesis. One set of alpha and
beta coefficients is required for each termination
impedance and balance network. These are provided
in the user manual. Alpha bits [9:0] represent the RC
time constant of the impedance that the filter is going to
synthesize. The bits are formatted as two’s comple-
ment. Alpha bits must be a nonzero value. Beta bits
[7:0] represent the dc gain of the filter. Beta coefficients
are also formatted as two’s complement. Setting beta
equal to zero turns off the CTZ function.
There is a constraint on the value of the protection
resistor with regard to termination impedance synthe-
sis and hybrid balance. For synthesis to operate prop-
erly, the total series Tip/Ring resistance must be 165
or greater. Coefficients for use with the L7585 SLIC are
set up for a protection value resistance of 82.5
in Tip
and 82.5
in Ring.
Loopback Modes
There are four loopback modes in the T7536.
The first two loopback modes are controlled by the all
channel test (ACT) register. ACT bits 0 and 1 place all
eight channels into loopback mode. Analog and digital
loopback are described and shown in block diagram
form in Table 29. Analog loopback allows one to check
functionality from Tip/Ring up to and including the
T7536. Digital loopback allows the T7531A to check
T7536 functionality.
The third loopback mode is used in the autocalibration
sequence (control register 2). This mode provides a
loopback between a selected channel and channel four
of a given T7536. The channel to be calibrated is
selected via control register 1 (see Table 27). Channel
four is the only channel in the T7536 that is trimmed for
gain accuracy. Every other channel uses channel four
as a reference and is calibrated to it during the autocal-
ibration sequence.
The fourth loopback mode is a digital loopback mode
located in control register 1. This operates like the digi-
tal loopback mode described in the notes for the ACT
register (Table 29). Unlike the ACT register, this digital
loopback mode is selectable per channel. This loop-
back mode can be used to check T7536 functionality
from the T7531A device. It is also used during the cali-
bration sequence.
There is one loopback mode in the T7531A. Loopback
at the oversampled data interface is controlled by board
control word 1. This mode allows the T7531A to test
itself. When bit 0 of 0x1FFE is selected, all 16 channels
of octal interface receive data (OSDRn) are looped
back to the T7531A transmit inputs (OSDXn).
Interchip Control Interface
The control interface is a 4-pin interface used to send
control information to the T7536 from the T7531A, and
to read back the control register contents. The pins
consist of a chip select input (CCS0/CCS1), a data
input (CDI), and a data output (CDO). The transfer of
control data is synchronous with the 4.096 MHz OSCK,
which is also used for oversampled data transfer.
T7531A Functional Blocks
Clock Synthesizer
The clock synthesizer block is a phase-lock loop (PLL)
circuit which takes SCK supplied by the backplane and
uses it to produce the 98.304 MHz DSP engine clock.
The input clock, SCK, can be 2.048 MHz or 4.096 MHz.
An on-chip clock synthesizer has the advantages
shown below:
I
Precludes the need for extra clocks to be fed over the
backplane.
I
Constrains the high-speed DSP engine clock within
the device.
I
Synchronizes all clocks used on the line card to the
backplane clock, thus reducing board noise due to
beat frequencies.
A clock generator block takes the PLL output and
divides it down to produce all the lower-frequency
clocks used by the T7531A and T7536.
T7531A System Interface
The system interface is a full-duplex interface used for
the exchange of PCM data with the system. The sys-
tem is the master of this bus. No control information is
transmitted over the system interface; all control
instructions are routed over the microprocessor inter-
face.
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