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參數資料
| 型號： | T7536 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組) |
| 中文描述： | 16通道可編程解碼器芯片組（十六通道可編程編解碼器芯片組） |
| 文件頁數： | 13/44頁 |
| 文件大?。?/td> | 772K |
| 代理商： | T7536 |
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Lucent Technologies Inc.
13
Data Sheet
February 1999
Codec Chip Set
T7531A/T7536 16-Channel Programmable
Chip Set Functional Description
(continued)
Receive Path
In the receive direction, the signal received from the sys-
tem interface is converted to a 16-bit linear PCM signal.
Receive Path Filtering
The 16-bit linear PCM signal is filtered and interpolated
to 16 ksamples/s to meet the receive signal loss charac-
teristics. This filter smooths the data following interpola-
tion from 8 ksamples/s to 16 ksamples/s.
Digital Receive Gain
The receive absolute and relative gains are specified as
15-bit binary numbers representing their linear magni-
tude. These gains default to 4000 Hex. This equates to
a 0 dB gain for the relative gain but equates to a
–0.211 dB gain for the absolute gain. For a 0 dB gain,
program the absolute gain for 4193 Hex. Gain can be
varied from minus infinity dB (0) (0000 Hex) to 6 dB rela-
tive gain or 5.8 dB absolute gain (7FFF Hex).
The relative gain control allows TLP adjustment without
hybrid balance or termination coefficient modification.
Interpolator and Digital Sigma-Delta Modulator
The sampling frequency of the receive signal from the
digital gain adjustment is increased from 16 kHz to
64 kHz by the interpolator, which removes most of the
high-frequency signal images above 8 kHz. The interpo-
lator also maps each of 16 time slots to the appropriate
line channel through the digital sigma-delta modulator.
The digital sigma-delta modulator converts the interpo-
lated signal to a 1.024 MHz bit stream which is then sent
to the T7536 device.
Decoder, Filters, and Receive Amplifier
Receive data enters the T7536 on pins OSDR[1:0] at
4.096 MHz; four channels are time-division multiplexed
onto each pin. The data is demultiplexed into eight indi-
vidual channels. The processed signal for each channel
passes through switched-capacitor D/A and reconstruct
filters, followed by a smoothing filter. A programmable
gain amplifier is included, followed by an output amplifier
capable of driving a 50 k
load to
±
1.58 V single-ended
(relative to VOS) or
±
3.16 V differential at peak over-
load. For single-ended operation, the load must be ac
coupled to VRP (or VRN).
Other Chip Set Functions
Voltage Reference
The T7536 has a precision on-chip voltage reference
which ensures accurate and highly stable transmission
levels.
Hybrid Balance
The hybrid
balance function is provided as a digital
block in the T7531A.
The T7531A implements a 9-tap FIR and a single-pole
IIR digital balance filter in which a replica of the echo is
digitally subtracted from the transmit plus near-end
echo signal. The coefficients are user programmable
on a per-line basis via the microprocessor interface.
Analog Termination Impedance Synthesis
Termination impedance matching is implemented to
maximize the power transfer capability at the loop inter-
face and to minimize signal reflections between the
transmit and receive paths.
The resistive component, implemented in the T7536
device, comprises a variable attenuated path between
VTX and VRP The capacitive component is imple-
mented in the digital domain.
Analog termination impedance (ATI) is provided with 16
gain settings to match a voltage drive/current sense
line interface circuit with the following characteristics:
Z
T
= 2R
P
+ G
TX
* G
RX
* A
T
where Z
T
is the termination impedance in ohms,
R
P
= 82.5
is the resistance of each protection resis-
tor, G
TX
is the SLIC transmit gain (300 V/A for the
L7585), G
RX
is the SLIC receive gain (2 for the L7585),
and A
T
is the T7536 feedback gain. The polarity of the
A
T
gain is positive (positive voltage swing on VTX gives
a positive voltage swing on VRP). The gain values and
the corresponding effective termination impedance are
shown in Table 26; gain tolerances are
±
2%. Differential
receive output is assumed.
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