參數(shù)資料
型號(hào)： T7531A
廠商： Lineage Power
元件分類： Codec
英文描述： 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組)
中文描述： 16通道可編程解碼器芯片組（十六通道可編程編解碼器芯片組）
文件頁(yè)數(shù)： 15/44頁(yè)
文件大?。?/td> 772K
代理商： T7531A
Lucent Technologies Inc.
15
Data Sheet
February 1999
Codec Chip Set
T7531A/T7536 16-Channel Programmable
Chip Set Functional Description
(continued)
T7531A Functional Blocks
(continued)
The system interface is used for all 16 lines serviced by
the T7531A. The PCM data rate is 8 ksamples/s/line,
so the total required channel capacity is 16 x 8 =
128 Kwords/s in each direction. At the 4.096 MHz rate,
each word takes 1.95
μ
s to transmit interleaved with
5.86
μ
s of dead time. The frame sync, SFS, is pre-
sented to the system interface at an 8 kHz rate.
A single bit clock and frame sync are used to control
both the transmit and receive directions. The beginning
of the first time slot in a frame is identified from the SFS
input (see Figure 9). In nondelayed mode, SFS is active
coincident with bit 0 of time slot 0 of the RX frame (and
the TX frame if the programmed offset between TX and
RX is 0). In delayed mode, SFS is active one cycle ear-
lier.
The amount of skew or offset between the transmit and
receive frames and time slots is programmable via
board control word 2, 0x1FFC. The bit offset is up to a
frame, i.e., up to 511 bits in 4 MHz mode. See Table 36
for a listing of invalid bit offset values. The bit offset
skew takes place in the system PCM interface block.
The active transmit and receive time slots are deter-
mined by the card address. The number of time slots
within a frame varies according to the rate of SCK. Only
16 time slots are ever active in a frame, as shown in
Table 3.
The T7531A obtains its card address in board control
word 1, 0x1FFE.
In
μ
-law or A-law mode, each PCM word is only 8 bits
long and occupies one time slot. In linear mode, the
PCM word is 16 bits long and occupies two adjacent
time slots. The MSB is the first bit clocked out in the
valid time slot, and the LSB is the last bit of the follow-
ing (invalid) time slot.
T7531A Microprocessor Interface
This interface between the microprocessor (or other
external controller) and the T7531A device carries
user-supplied program variables and control and test
instructions to both the T7531A and the T7536 octal
converters. The external device is the master of the
microprocessor interface. The interface is serial and
asynchronous, and consists of four pins (UPCK,
UPCS, UPDI, UPDO). The data rate is determined by
the customer’s choice of external device, but may not
exceed 4.096 MHz. Microprocessor interface com-
mands consist of two words, address and data.
Address and data are 16 bits wide. The T7531A
expects an address first. The first bit of the address
word is the R/W flag, which tells the T7531A whether
it must receive or send data (receive, R/W = 0; send,
R/W = 1).
Addresses less than 0x1400 refer to the DSP engine
RAM space. If a read from the DSP engine is required,
the microprocessor interface issues a read interrupt to
the DSP engine. If it's a write to the DSP engine, the
microprocessor interface shifts in the data word and
saves it into the data register before sending a write
interrupt to the DSP engine. Once in every 7.8
μ
s time
segment, the DSP engine checks whether an interrupt
is outstanding from the microprocessor interface block.
If so, the DSP engine reads the address register. If it's
a read, the DSP engine fetches the word from RAM,
places it in the data register, and shifts it out to the
microprocessor. If it's a write, it puts the contents of the
data register into RAM.
A pause therefore exists between the external control-
ler issuing an address and receiving a data read back.
The data rate of 2.048 MHz allows 256 SCK cycles in a
frame, i.e., eight address/data pairs with no pause
between words. Since the DSP engine can process
only one interrupt every 7.8
μ
s, the T7531A requires a
separation between address and data on read and
write instructions to the microprocessor interrupt (see
Figure 10). This, in effect, requires UPCK to be
gapped.
Table 3. Active Time-Slot Spacing in a PCM Bus Frame
SCK Rate (MHz)
2.048
Total # of Time Slots
32
Card Address
0
1
0
1
2
3
Valid Time Slots
0, 2, 4, . . . 30
1, 3, 5, . . . 31
0, 4, 8, . . . 60
1, 5, 9, . . . 61
2, 6, 10, . . . 62
3, 7, 11, . . . 63
Invalid Time Slots
1, 3, 5, . . . 31
0, 2, 4, . . . 30
1—3, 5—7, . . . 61—63
0, 2—4, 6—8, . . . 62—63
0—1, 3—5, 7—9, . . . 63
0—2, 4—6, 8—10, . . . 60—62
4.096
64
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