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參數(shù)資料
| 型號： | T7531A |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組) |
| 中文描述： | 16通道可編程解碼器芯片組（十六通道可編程編解碼器芯片組） |
| 文件頁數(shù)： | 10/44頁 |
| 文件大小： | 772K |
| 代理商： | T7531A |
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10
Lucent Technologies Inc.
Data Sheet
February 1999
Codec Chip Set
T7531A/T7536 16-Channel Programmable
Pin Information
(continued)
Table 2. T7531A Pin Descriptions
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; I
u
indicates a pull-up
device is included on this lead.
Number
22
Name
UPDI
Type
TI
Name/Function
Control Data Interface Input.
The microcontroller sends control register
address and data to the T7531A through this pin.
Control Data Interface Output.
The microcontroller receives control regis-
ter contents from this pin. Inactive state is high impedance.
Control Data Interface Clock.
Bit clock for the control interface. Speed is
limited to 4.096 MHz.
Control Interface Chip Select (Active-Low).
This active-low input enables
the control interface.
Oversampled Transmit Data.
Four channels of 1 Msamples/s
Σ
-
transmit
data are received from the T7536 chips through each of these pins. The data
rate is 4.096 MHz.
Oversampled Receive Data.
Four channels of 1 Msamples/s
Σ
-
receive
data is transmitted to the T7536 chips on each of these pins. The data rate is
4.096 MHz.
4.096 MHz Clock.
Clock for data transfer to/from T7536 chips.
Oversampling Sync.
8 kHz synchronization pulse for data transfer
to/from T7536 chips.
Filter.
External filter pin for the clock synthesizer block. Connect a 6.8 k
,
10% resistor in series with a 0.1
μ
F, 20% capacitor to ground. Placement of
these components is not as critical as power supply decoupling capacitor
placement.
Filter.
External filter pin for the clock synthesizer block. Connect a 6.8 k
,
10% resistor in series with a 0.1
μ
F, 20% capacitor to ground. Placement of
these components is not as critical as power supply decoupling capacitor
placement.
Filter.
External filter pin for the clock synthesizer’s voltage regulator. Connect
a 0.1
μ
F, 20% capacitor to ground.
Synthesizer V
DD
.
Power supply for clock synthesizer block.
Synthesizer Ground.
Ground connection for the clock synthesizer block.
Backplane Drive Enable (Active-Low).
Active when SDX is transmitting
valid data; high impedance otherwise. This pin provides an enable signal for
a backplane line driver.
Master Clock Input.
This is the bit clock used to shift data into and out of the
SDR and SDX pins. It is the input to the clock synthesizer and is used to gen-
erate all internal clocks. Rate is 4.096 MHz.
Master Clock Select Input.
A logic low selects the 2.048 MHz SCK. A logic
high selects the 4.096 MHz SCK. An internal pull-up device is included, pro-
viding 4.096 MHz SCK operation with no external connections.
Receive PCM Input.
The data on this pin is shifted into the T7531A on the
falling edges of SCK. Data is only entered for valid time slots as defined in
the TSA registers.
23
UPDO
TO
20
UPCK
TI
21
UPCS
TI
38, 40,
31, 33
OSDX[3:0]
CI
37, 39,
30, 32
OSDR[3:0]
CO
34
35
OSCK
OSFS
CO
CO
4
FILT1
—
5
FILT2
—
7
FILT3
—
3
6
17
FV
DD
FV
SS
STSXB
—
—
TO
13
SCK
TI
10
SCKSEL
TI
u
15
SDR
TI
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