參數(shù)資料
型號(hào)： T7531A
廠商： Lineage Power
元件分類： Codec
英文描述： 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組)
中文描述： 16通道可編程解碼器芯片組（十六通道可編程編解碼器芯片組）
文件頁(yè)數(shù)： 11/44頁(yè)
文件大小： 772K
代理商： T7531A
Lucent Technologies Inc.
11
Data Sheet
February 1999
Codec Chip Set
T7531A/T7536 16-Channel Programmable
Pin Information
(continued)
Table 2. T7531A Pin Descriptions
(continued)
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; I
u
indicates that a pull-up
device is included on this lead.
Number
16
Name
SDX
Type
TO
Name/Function
Transmit PCM Output.
This pin remains in the high-impedance state
except during the transmit time slots as defined in the TSA registers.
Data is shifted out on the rising edge of SCK.
Frame Sync.
Active-high pulse or square wave with an 8 kHz pulse
repetition rate. The rising edge defines the start of the transmit and
receive frames.
T7536 Control Data Output
. Control register information for the T7536
chips. Data is valid only when either CCS0 or CCS1 is low.
T7536 Control Data Input
. Control register information from the T7536
chips. Data is valid only when either CCS0 or CCS1 is low. An internal
pull-up device is provided.
Control Interface Chip Select.
These active-low outputs select one of
the associated T7536 chips.
JTAG Common Test Clock.
Rate
≤
20 MHz.
JTAG Serial Data Input.
A pull-up device is provided.
JTAG Serial Data Output.
JTAG Mode Select.
A pull-up device is provided.
3-State Control Pin (Active-Low).
When pulled low, the device output
pins go into a high-impedance state. A pull-up device is provided.
Test Mode Input (Active-Low).
This input allows bypass of clock synthe-
sizer and uses TSTCLK to drive the chip. A pull-up device is provided.
16 MHz Clock Output.
16 MHz clock output (50% duty cycle).
Test Clock.
Test mode 98.304 MHz clock input for bypass of clock syn-
thesizer.
No Connect.
Do not make any connections to these pins.
14
SFS
TI
50
CDO
CO
47
CDI
TI
u
49, 48
CCS[1:0]
CO
67
64
65
66
55
TCK
TDI
TDO
TMS
HIGHZB
TI
TI
u
TO
TI
u
TI
u
56
TEST
CI
u
57
68
CK16
TSTCLK
CO
CI
26, 27, 43, 44,
60, 61
51
NC
—
T_SYNC
CI
u
Test Sync (Active-Low).
Used for factory testing. Do not make any con-
nection to this pin. A pull-up device is provided.
Reset (Active-Low).
A logic low initiates reset. A pull-up device is pro-
vided.
+5 V Digital Power Supply.
Power supply decoupling capacitors (0.1
μ
F)
should be connected from each V
DD
pin to ground. Capacitors should be
located as close as possible to the device pins.
Digital Ground.
54
RSTB
TI
u
2, 9, 12, 18, 24,
29, 41, 46, 52,
58, 63
1, 8, 11, 19, 25,
28, 36, 42, 45,
53, 59, 62
V
DD
—
V
SS
—
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