參數(shù)資料
型號(hào)： T431616B-20C
廠商： TM Technology, Inc.
英文描述： 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
中文描述： 100萬(wàn)× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM
文件頁(yè)數(shù)： 26/31頁(yè)
文件大小： 567K
代理商： T431616B-20C
TE
CH
tm
Burst Read Single bit Write Cycle @ Burst Length = 2
T431616B
Taiwan Memory Technology, Inc. reserves the right
P.26
to change products or specifications without notice.
Publication Date: JUL. 2001
Revision:A
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
D Q M
D Q
: D o n ' t c a r e
*Note2
R A a
C A a
R B b
C A b
R A c
C B c
C A d
R A a
R B b
R A c
DAa0
DAa0
DAb0
DAb0
DAb1
DAb1
D B c 0
D B c 0
DAd0
DAd1
DAd0
DAd1
Row Active
(A-Bank)
Write (A-
Bank)
Row Active
(A-Bank)
Read with Auto
Precharge (A-
Bank)
Row Active
(A-Bank)
Write with Auto
Precharge (A-
Bank)
Read (A-
Bank)
Precharge
(A-Bank)
*Note : 1. BRSW modes is enabled by setting A
9
‘High’ at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to ‘1’ regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that
t
RAS
should not
be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command,
the precharge command will be issued after two clock cycle.
相關(guān)PDF資料
PDF描述
T431616B-20S 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616C 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616C-6S 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T431616B-20S 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616C 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616C-6S 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616C-6SG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616C-7S 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
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