參數(shù)資料
型號(hào)： SYM53C141
廠商： LSI CORP
元件分類： 微控制器/微處理器
英文描述： SCSI Bus Expander(SCSI總線擴(kuò)展器)
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP128
封裝： PLASTIC, QFP-128
文件頁數(shù)： 28/68頁
文件大?。?/td> 630K
代理商： SYM53C141
2-10
Functional Description
2.
The next stage is a leading edge filter. This ensures that the output
does not switch for a specified time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3.
A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.7.7 Clock (CLOCK)
This is the 40 MHz oscillator input to the SYM53C141. This is the clock
source for protocol control state machines and timing generation logic.
This clock is not used in any bus signal transfer paths.
2.7.8 Chip Reset (RESET/)
This general chip reset is intended to force all the internal elements of
the SYM53C141 into a known state. This brings all state machines to an
idle state and force all controls to a passive state. The minimum RESET
input asserted pulse width is 100 nanoseconds.
The SYM53C141 also contains an internal Power On Reset (POR)
function that is wire ORed with the chip reset pin. This function
eliminates the need for an external chip reset.
2.7.9 Warm SWAP Enable and Transfer Active (WS_ENABLE and
XFER_ACTIVE)
These two pins provide additional control capability for the SYM53C141.
They allow both the SCSI A-side bus and the SCSI B-side bus to be
logically disconnected. The XFER_ACTIVE output changes state only
with the detection of a SCSI bus free state; this guarantees that transfers
Table 2.2
RESET/ Control Signal Polarity
Signal Level
State
Effect
LOW = 0
Asserted
Reset is forced to all internal SYM53C141
elements.
HIGH = 1
Deasserted
SYM53C141 is not in a forced reset state.
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