- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385894 > SYM53C141 (LSI CORP) SCSI Bus Expander(SCSI總線擴展器) PDF資料下載
參數(shù)資料
| 型號： | SYM53C141 |
| 廠商： | LSI CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SCSI Bus Expander(SCSI總線擴展器) |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 630K |
| 代理商： | SYM53C141 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
Signal Descriptions
2-7
The SYM53C141 receives data and parity signals and passes them from
the source bus to the load bus and provides any necessary edge shifting
to guarantee the skew budget for the load bus. Either side of the
SYM53C141 can be the source bus or the load bus. The side asserting,
deasserting or releasing the SCSI signals is the source side. The
following steps are a part of the SYM53C141 data path:
1.
Asserted data is accepted from the receiver logic as soon as it is
received. Once the clock signal has been received, data is gated
from the receiver latch.
2.
The path is tested to ensure the signal, if being driven by the
SYM53C141, is not misinterpreted as an incoming signal.
3.
The data is then leading edge filtered. The assertion edge is held for
a specified time to prevent any signal bounce. The duration is then
controlled by the input signal.
4.
The next stage is a latch that samples the signal. This provides a
stable data window for the load bus.
5.
The final stage develops pull-up and pull-down controls for the SCSI
I/O logic, including 3-state controls for the pull-up.
6.
A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.7.2 Busy (BSY) Control
A_SBSY/ and B_SBSY
±
signals are propagated from the source bus to
the load bus. These signals go through the following processing steps:
1.
The path is tested to ensure the signal, if being driven by the
SYM53C141, is not misinterpreted as an incoming signal.
2.
The data is then leading edge filtered. The assertion edge is held for
a specified time to prevent any signal bounce. The duration is then
controlled by the input signal.
3.
The next stage has two modes. One mode simply passes data
through. The other mode behaves like a large filter. The current state
in the SYM53C141 state machine that tracks SCSI phases selects
the mode. The large filter mode is used where the Busy (BSY) and
Select (SEL) sources may switch from side to side. This output is
then fed to the output driver which is a pull-down open collector only.
相關PDF資料 |
PDF描述 |
|---|---|
| SYM53C180 | Ultra3 SCSI Bus Expander(Ultra2 SCSI總線擴展器) |
| SYM53C710 | 32-Bit SCSI I/O Processor(32位SCSI I/O處理器) |
| SYM53C770 | SCSI I/O Processor With Ultra SCSI(帶超級SCSI的SCSI I/O處理器) |
| SYM53C810A | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| SYM53C825A | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SYM53C400A | 制造商:SYMBIOS 功能描述: |
| SYM53C770 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C876E(PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C876E(PQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C885 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。