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參數(shù)資料
| 型號： | STW5094ADT/LF |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 18-BIT DAC, PBGA36 |
| 封裝： | 6 X 6 MM, 1.2 MM HEIGHT, TFBGA-36 |
| 文件頁數(shù)： | 6/52頁 |
| 文件大?。?/td> | 596K |
| 代理商： | STW5094ADT/LF |
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Example: The master clock frequency is fAMCK=12MHz, the required sampling frequency is fL-
RCK=44.1kHz, N value is:
30828 decimal corresponds to 786C hex so CR2B and CR3B must be loaded with 6C hex and 78 hex
respectively, the frequency of LRCK will then be:
2.15 OCK output clock generation
Setting OCE = 1 and SPIM =0 in CR17 enables the internal generation of the clock OCK on the pin
REMOUT
OCK. The clock output can be used as master clock for a digital device that provides the Au-
dio Data to STw5094A.
This function is compatible with both Master mode and Slave mode of the Au I
F and can be used in
Normal mode and in DSP mode while it cannot be used in SPI mode. It can be activated also in Voice
mode (provided the AMCK clock is available).
Because OCK clock is obtained by variable division from the master clock AMCK, OCK cannot have a
frequency higher than the AMCK master clock frequency.
When OCK frequency is comprised between AMCK frequency and half the AMCK frequency OCK is ob-
tained removing pulses, as evenly spaced as possible, from AMCK and thus reducing the frequency to
the programmed value. When OCK frequency is lower than half AMCK frequency it is obtained by division
on the rising edge of AMCK.
OCK polarity can be inverted setting ROI =1 in CR17.
OCK in Master Mode: when the Au I
F is used in Master Mode the OCK frequency is 256 times the
sampling frequency programmed in CR2B and CR3B using the formula described in Section 2.14
(
fOCK = 256 fLRCK).
OCK in Slave Mode: when the Au I
F is used in Slave Mode the OCK frequency can be set to any value
(lower than AMCK frequency) and it is not related to the incoming LRCK frequency, then not limited to
256 oversampling. In this case to obtain the desired OCK frequency the following formula can be used:
where
fOCK is lower than fAMCK (this corresponds to the fact that N cannot be greater than 7FFF hex).
Example: The master clock frequency is fAMCK=19.2MHz, the oversampling factor is 384 and the sam-
pling rate is 44.1 kHz, then the required OCK frequency is
fOCK = 384 44.1 kHz = 16934400 Hz.
The value of N is:
28901 decimal corresponds to 70E5 hex so CR2B and CR3B must be loaded with E5 hex and 70 hex
respectively, the frequency of OCK will then be
The OCK output clock function is alternative to the Remocon function because both share the same output
pin: setting OCE = 1 will disable the Remocon function on the REMOUT
OCK but the REMOCON out-
put status will still be available reading bit RDL in CR17 (see paragraph II.18 for more details on REMO-
CON function).
Since CR2B and CR3B are overlaid registers, in order to write the division factor N in CR2B and CR3B,
the output clock function must be selected in advance by setting OCE =1.
N = round(223(44100
12000000)) = 30828
fLRCK = (3082812000000 Hz)
223 = 44099.8 Hz.
N = round(215(fOCK
fAMCK))
N = round(215(16934400
19200000)) = 28901
fOCK = (2890119200000 Hz)
215 = 16934179.7 Hz = 384 44099.4 Hz
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| STW5094AD/LF | SERIAL INPUT LOADING, 18-BIT DAC, PBGA36 |
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| SU-1/2-B2 | POWER TRANSFORMER, 500 VA |
| SU-1/4-B1 | POWER TRANSFORMER, 250 VA |
| SU-10-B8 | POWER TRANSFORMER, 10000 VA |
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參數(shù)描述 |
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