參數(shù)資料
型號: STW5094ADT/LF
廠商: STMICROELECTRONICS
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 18-BIT DAC, PBGA36
封裝: 6 X 6 MM, 1.2 MM HEIGHT, TFBGA-36
文件頁數(shù): 14/52頁
文件大?。?/td> 596K
代理商: STW5094ADT/LF
20/51
Control Register CR15 Functions (Address: 0x0F)
* state at power on initialization
Control Register CR16 Functions (Address: 0x10)
(1) significant in 18
20 24 bit per word mode only
(2) Left Channel data is always received first.
(3) First bit delay, in 18
20 24 bit per word mode, is applied only if word is left justified.
*: state at power on initialization
7654
3210
Function
BE
BI
BZ(5:0)
0
1
Buzzer output disabled (set to 0)
*
Buzzer output enabled
0
1
Duty Cycle is intended as the relative width of logic 1
*
Duty cycle is intended as the relative width of logic 0
msb
lsb
Binary equivalent of the decimal number used to calculate the
duty cycle, using the formula:
Duty Cycle = BZ(5:0) x 0.78125%
7654
3210
Function
POL
ORD
DIF
INV
FOR
SCL
PREC(1:0)
0
1
AMCK Not Inverted
*
AMCK Inverted
0
1
Audio I/F data order, the MSB is received first (I2S)
*
Audio I/F data order, the LSB is received first
0
1
Audio I/F data alignment, the word is left justified (I2S)(1) *
Audio I/F data alignment, the word is right justified
(1)
0
1
LRCK polarity, when LRCK=0 Left data is received
(I2S) (2) *
LRCK polarity, when LRCK=1 Left data is received
(2)
0
1
Audio I/F format, I2S format (first bit is delayed)
(3) *
Audio I/F format, non delayed formats
0
1
SCK polarity, SDI and LRCK sampled on the rising edge
(I2S)
*
SCK polarity, SDI and LRCK sampled on the falling edge
0
1
0
1
0
1
Audio I/F data width 16 bit (32 SCK clocks per frame)
*
Audio I/F data width 18 bit (64 SCK clocks per frame)
Audio I/F data width 20 bit (64 SCK clocks per frame)
Audio I/F data width 24 bit (64 SCK clocks per frame)
相關(guān)PDF資料
PDF描述
STW5094AD/LF SERIAL INPUT LOADING, 18-BIT DAC, PBGA36
SU-1-B3 POWER TRANSFORMER, 1000 VA
SU-1/2-B2 POWER TRANSFORMER, 500 VA
SU-1/4-B1 POWER TRANSFORMER, 250 VA
SU-10-B8 POWER TRANSFORMER, 10000 VA
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