參數(shù)資料
型號: STW5094
廠商: 意法半導(dǎo)體
元件分類: Codec
英文描述: 18 BIT 8kHz TO 48kHz LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODEC
中文描述: 18位8kHz至48kHz的低功耗立體聲音頻DAC,具有集成功率放大器和語音編解碼器
文件頁數(shù): 9/37頁
文件大?。?/td> 447K
代理商: STW5094
9/37
STw5094
II.11
Audio Data Interface (I
2
S I
F):
The I
2
S I
F is used to receive the Left and Right channel Audio data (see Fig. 4 and 5). The interface is I
2
S
compatible and can be configured in other different modes writing
CR16
.
When the I
2
S I
F is active (Audio mode) the Master Clock of the device is
OCK
. The frequency of
OCK
is 256
times the sampling frequency (
LRCK
frequency) when the sampling frequency is between 16kHz and 48kHz
(
LAY(1)
= 0 in
CR6
), and 512 times when the sampling
frequency is between 8kHz and 12kHz (
LAY
= 10 in
CR6
). The polarity of
OCK
can be selected
.
SCK
frequency is 32 times the
LRCK
one in case of 16bit Data word and 64 times in case of 18bit to 24bit Data
word. Left channel data are always received first, the polarity of
LRCK
can be selected.
The first 35 Data frames after power up are discarded while the interpolation filters data memory is cleared.
II.12
Control Interface (I
2
C I
F):
The I
2
C I
F is used to program the device by writing and reading the control registers (see Fig 6 and 7). The
interface is I
2
C bus compatible, being the STw5094 a Slave device.
SDA
is the bidirectional open-drain data pin
and
SCL
is the input clock pin. The Device Address is E2 hex. for writing and E3 hex. for reading.
The interface has an internal address register that keeps the current address of the control register to be read
or written. At each write access of the interface the address register is loaded with the data of the register
address field. The value in the address register is increased after each data byte read or write. It is possible to
access the interface in 2 modes: single-byte mode in which the address and data of a single register are
specified, and multi-byte mode in which the address of the first register to be written or read is specified and all
the following bytes exchanged are the data of successive address registers starting from the one specified (in
multi-byte mode the internal address counter restart from register 0 after the last register 18). Using the
multi-byte mode it is possible to write or read all the registers with a single access to the device on the I
2
C bus.
The Control interface can be used both in power-up and power-down state.
II.13
Master Clock in FM mode and Tone Only modes:
In FM mode and in Tone Only mode the Master Clock of the device can be selected to be
AUXCLK
,
MCLK
or
OCK
writing bits
CFM
in
CR18
. The Auxiliary clock
AUXCLK
can be used when the Audio mode clock
OCK
and the Voice mode clock
MCLK
are not available.
AUXCLK
and
MCLK
frequency selection is done with bits
F
in
CR0
.
II.14
REMOCON function:
The REMOCON (Remote Control) function can be used to detect the status of an headset button. The
REMOCON function is enabled by setting bit
REN
in
CR17
. If enabled, this function is active also when the
STw5094 is in power-down state.
A High level at
REMIN
input is detected as a non pressed button, while a low level is detected as a pressed
button. The "Pressed Button" information can be treated in 2 ways depending on bit
RLM
in
CR17
:
- if
RLM
= 0 (Transparent mode) the information at
REMIN
is seen at
REMOUT
after a debounce time of 50ms
maximum;
- if
RLM
= 1 (Latched Mode) the information stored in bit
RDL
in
CR17
is seen at
REMOUT
.
RDL
is set after a
debounce time of 50ms maximum when a low level at
REMIN
is detected.
RDL
is reset with power on
initialization and can also be reset writing 0 in bit
RDL
.
The
REMOUT
output polarity can be inverted setting bit
ROI
in
CR17
: the pressed button information is
presented at
REMOUT
output as a logic 1 if bit
ROI
= 0. If
ROI
= 1 the polarity is inverted.
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