- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382569 > STW5094 (意法半導(dǎo)體) 18 BIT 8kHz TO 48kHz LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODEC PDF資料下載
參數(shù)資料
| 型號(hào)： | STW5094 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | 18 BIT 8kHz TO 48kHz LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODEC |
| 中文描述： | 18位8kHz至48kHz的低功耗立體聲音頻DAC，具有集成功率放大器和語(yǔ)音編解碼器 |
| 文件頁(yè)數(shù)： | 23/37頁(yè) |
| 文件大小： | 447K |
| 代理商： | STW5094 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)
23/37
STw5094
PCM Interface Timing
I
2
C Bus Control Port Timing
Note:
A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH.For the purpose of this specification the
following conditions apply (see Fig. 8):
a) All input signal are defined as: VIL = 0.2VCCIO, VIH = 0.8VCCIO, tR < 10ns, tF < 10ns.
b) Delay times are measured from the inputs signal valid to the output signal valid.
c) Setup times are measured from the data input valid to the clock input invalid.
d) Hold times are measured from the clock signal valid to the data input invalid.
Symbol
Test Condition
Min.
Typ.
Max.
Unit
t
HMF
Hold Time MCLK low to FS low
10
ns
t
SFM
Setup Time, FS high to MCLK low
30
ns
t
DMD
Delay Time, MCLK high to data
valid
Load = 20pF
100
ns
t
DMZ
Delay Time, MCLK low to
DX disabled
10
100
ns
t
DFD
Delay Time, FS high to data valid
Load = 20pF; Applies only if FS
rises later than MCLK rising edge
in Non Delayed Mode only
100
ns
t
SDM
Setup Time, DR valid to MCLK
receive edge
20
ns
t
HMD
Hold Time, MCLK low to DR
invalid
10
ns
t
HMFR
Hold Time MCLK High to FS low
30
ns
t
SFMR
Setup Time, FS high to MCLK
High
30
ns
t
DMDR
Delay Time, MCLK low to data
valid
Load = 20pF
100
ns
t
DMZR
Delay Time, MCLK High to DX
disabled
10
100
ns
t
HMDR
Hold Time, MCLK High to DR
invalid
20
ns
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
f
SCL
Clock Frequency
400
kHz
t
HIGH
Clock High Time
600
ns
t
LOW
Clock Low Time
1300
ns
t
R
SDA and SCL Rise Time
1000
ns
t
F
SDA and SCL Fall Time
300
ns
t
HD:STA
Start Condition Hold Time
600
ns
t
SU:STA
Start Condition Setup Time
600
ns
t
HD:DAT
Data Input Hold Time
0
ns
t
SU:DAT
Data Input Setup Time
250
ns
t
SU:STO
Stop Condition Setup Time
600
ns
t
BUF
Bus Free Time
1300
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STW50N10 | N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR |
| STW50NB20 | N - CHANNEL 200V - 0.047ohm - 50A - TO-247 PowerMESH MOSFET |
| STW5NB100 | N-Channel 1000V-4Ω-4.3A- TO-247 PowerMESHTM MOSFET(N溝道MOSFET) |
| STW60NE10 | N - CHANNEL 100V - 0.016ohm - 60A TO-247 STripFET POWER MOSFET |
| STW60N10 | CAP 330PF 200V 1% NP0(C0G) DIP-2 TUBE-PAK R-MIL-PRF-39014/22 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STW5094A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:18-bit Low Power Asynchronous Stereo Audio DAC with Integrated Power Amplifiers and Voice Codec |
| STW5094A_05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:18-bit Low Power Asynchronous Stereo Audio DAC with Integrated Power Amplifiers and Voice Codec |
| STW5094AD | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:18-bit Low Power Asynchronous Stereo Audio DAC with Integrated Power Amplifiers and Voice Codec |
| STW5094AD/LF | 功能描述:音頻 DSP 18B Lo Pwr async stereo audio DAC RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| STW5094ADEMO | 制造商:STMicroelectronics 功能描述:5962F8974902VXA - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。