參數(shù)資料
型號(hào)： STW5094
廠商： 意法半導(dǎo)體
元件分類： Codec
英文描述： 18 BIT 8kHz TO 48kHz LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODEC
中文描述： 18位8kHz至48kHz的低功耗立體聲音頻DAC，具有集成功率放大器和語音編解碼器
文件頁數(shù)： 8/37頁
文件大?。?/td> 447K
代理商： STW5094
STw5094
8/37
programming bits
OS
in
CR6
. These settings are not dependent from the selected operative Mode. If
HPL
and
HPR
are enabled together in Voice Mode or Tone Only Mode the same signal is sent to both Drivers. The active
Drivers can be muted (keeping them in power-up state) using bit
MUT
in
CR7
. At power-up or after a change in
OS
bits the outputs are muted for 10 ms to avoid unwanted noise. The transient suppression filter is used to
avoid clicks when the gain value is changed.
II.8
Tone Generator:
The Tone Generator can be activated (writing
CR12
) in all the Stw5094 operating modes except FM mode. In
Voice and Audio modes the tones are summed to the signal. It is possible to generate 1 or 2 summed waveforms
(either sinusoidal or square wave), their frequencies can be set in
CR13
for the first one (f1) and in
CR14
for the
second one (f2) accordingly to the values listed in Table 1. The amplitude of the generated waveform can be
regulated in
CR12
over a 33dB range. When both f1 and f2 are selected the amplitude of f1 and f2 are lowered
by 5dB and 7dB respectively with respect to the amplitude of a single waveform. In this way the amplitude of
the summed waveforms does not overload and there is a 2dB difference between f1 and f2 amplitude as
required for DTMF generation. The Tone Generator output can be sent to the Voice Transmit section (in Voice
Mode), to the Power amplifiers, possibly mixed with audio or voice, (in all the modes except FM mode) and to
the buzzer output
BZ
(in all the modes except FM mode).
II.9
Buzzer Output:
The output
BZ
is intended to drive a Buzzer, via an external BJT, with a squarewave pulse width modulated
(PWM) signal. The frequency of the signal is stored in
CR13
(see Table1 for frequency values). For some
applications it is also possible to multiply this PWM signal with a squarewave signal having a frequency stored
in
CR14
. The duty cycle of the buzzer output can be varied in
CR15
in order to change the buzzer volume.
Maximum load for
BZ
is 5k
and 50pF.
II.10
Voice Data Interface (PCM I
F):
The PCM I
F is used to exchange the Voice data in both TX and RX direction, it can be programmed for linear
format data or companded A-law or
μ
-law format (see Fig.1, 2 and 3).
Frame Sync input
FS
determines the beginning of frame. It may have any duration from a single cycle of
MCLK
to a squarewave. Three different relationships may be established between the Frame Sync input and the first
time slot of the frame by setting bits
DM
in
CR1
. In non delayed normal and reverse data mode (long frame
timing) the first time slot starts at the rising edge of FS. In delayed data mode (short frame sync timing)
FS
input
must be high for at least a half cycle of
MCLK
before the frame start.
When linear code is selected (bit
CM
= 0 in
CR0
) the MSB is transmitted and received first, the word length is
16 bit. When companded code is selected (bit
CM
= 1 in
CR0
) a time slot assignment may be used in all timing
modes (bit
TS
in
CR1
), that allows connection to one of the two B1 and B2 voice data channels. Two data
formats are available: in Format 1, time slot B1 corresponds to the 8
MCLK
cycles that immediately follow the
rising edge of
FS
, while time slot B2 corresponds to the 8
MCLK
cycles that immediately follow time slot B1. In
Format 2, time slot B1 is identical to Format 1 while time slot B2 appears two bit slots after time slot B1. This
two bits space is left available for insertion of the D channel data. Data format is selected by bit
FF
in
CR0
.
Bit
EN
in
CR1
enables or disables data transfer on
DX
and
DR
.
Outside the selected time slot
DX
is in the high impedance condition. During the selected time slot the
DX
output
and the
DR
input are synchronized as follow:
-If delayed or non-delayed modes are selected the transmit voice data is sent to
DX
output on the rising edges
of
MCLK
and receive voice data is read at
DR
input on the falling edges of
MCLK
.
-If non-delayed reverse mode is selected the transmit voice data register is sent to
DX
output on the falling
edges of
MCLK
and receive voice data is read at
DR
input on the rising edges of
MCLK.
When 16kHz Frame Sync frequency is selected (bit
VFS
in
CR0
) the RX and TX filters are both low-pass and
their cutoff frequencies are doubled.
It is possible to access the B channel data when companded A-law or
μ
-law formats are used (bits
MX
and
MR
in
CR1
). A byte written into
CR3
will be sent to
DX
output in place of the transmit channel PCM data. A byte
written in
CR2
will be sent to the receive path. The current byte received on
DR
input can be read in
CR2
.
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