參數(shù)資料
型號： STV9212
廠商： 意法半導(dǎo)體
英文描述： Video Processor for CRT Monitors with PictureBooST
中文描述： 視頻處理器PictureBooST的CRT顯示器
文件頁數(shù)： 6/34頁
文件大小： 335K
代理商： STV9212
Functional Description
STV9212
6/34
2.1
Video RGB Input Clamp
The three RGB inputs have to be supplied with a video signal through coupling capacitors playing
the role of analog memories for internal video clamps. The input clamping level is approximately 0V.
The clamp is gated by the Input Clamp Pulse (ICP) that is internally generated from a signal on
either the HS or BLK pin. The selection is done via register 8 of the I2C-bus. For more information,
refer to
Figure 3: ICP, OCP and BLKI Generation
and
Table 2: ICP Timing
.
Provided with an automatic polarity rectification function, the HS input accepts horizontal
synchronization signals of either polarity. The device can select either the leading or trailing edge of
this signal to trigger the ICP generator.
The BLK input is followed by an inverter stage that can be enabled or by-passed via the I2C-bus.
This allows the use of a signal of either polarity, the control software taking care of the inverter
position according to the signal applied. The BLKI signal found behind this inverter stage also drives
the video blanking circuitry which requires a positive BLKI polarity for correct operation. Once bit
BLKPOL
has correctly been uploaded to ensure a positive BLKI polarity, the ICP triggering edge
can be selected via control bit
BCEDGE
. A horizontal flyback pulse is generally expected to be
applied on the BLK input. As the edges of horizontal flyback pulse can fall into the active video
content (outside the video signal line blanking portion), the application must ensure that such an
edge is never selected for triggering the ICP.
The width of the internally generated ICP is controlled via the I2C-bus. The HS input can be used to
pass a clamping pulse, if available in the application, directly to clamping stages, without any
additional processing. In this case, the appropriate polarity (positive) is required.
See
Table 2: ICP
Timing
.
The ICP timings triggered by the trailing edge of the BLK signal are not presented.
The Output Clamp Pulse (OCP) is described in
Section 2.8: Output Stage
.
Figure 3: ICP, OCP and BLKI Generation
HS
Pulse
Generation
on
BLK
ICP
(Internal)
OCP
(Internal)
BLKPOL
(Sad09/b0)
ICP width
BCWDTH
(Sad08/b2,b3)
2
24
-1
0
1
BCEDGE
(Sad08/b1)
-1
0
1
0
1
Automatic
Polarity
BCSC0
(Sad08/b0)
Pulse
Generation
on
OCPSC
(Sad08/b7)
BCSC1
(Sad08/b4)
0
1
0
1
Note: The I2C-bus switches are displayed in their default positions
Video blanking
ICP trig/pulse mode
BLKI
(Internal)
BLKI
I2C-bus field
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