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參數(shù)資料
| 型號： | STV9212 |
| 廠商： | 意法半導體 |
| 英文描述： | Video Processor for CRT Monitors with PictureBooST |
| 中文描述： | 視頻處理器PictureBooST的CRT顯示器 |
| 文件頁數(shù)： | 20/34頁 |
| 文件大?。?/td> | 335K |
| 代理商： | STV9212 |
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I2C-Bus Interface Specifications
STV9212
20/34
3
I2C-Bus Interface Specifications
The device is compatible to general I2C-bus specification. Its slave write address is DCh.
Subaddress (Sad) auto-incrementing is not available. Only Write mode is supported. The control
register map is given in
Table 4
.
Bold
weight denotes default values assumed at power-on reset. The power-on reset is effected
every time that the supply voltage on VCCA pin drops below V
PORTH
threshold (Refer to electrical
specifications).
In order to ensure compatibility with future devices, all “Reserved” bits are to be set to 0 once
uploaded by the control software.
Table 4: I2C-Bus Register Map
Sad
b7
b6
b5
b4
b3
b2
b1
b0
01
CRST
0
Reserved
0
1
0
0
0
0
0
02
BRIG
1
0
0
0
0
0
0
0
03
DRIVE1
0
DRIVE2
0
DRIVE3
0
Reserved
0
Reserved
0
Reserved
0
1
0
0
0
0
0
04
1
0
0
0
0
0
05
1
0
0
0
0
0
06
Reserved
BRIGRG
0
0
0
0
0
0
0
1
07
Reserved
OSDCRST
0
0
0
0
1
0
0
1
08
OCPTG
0
:BLK
1:ICP
ASTBY
0
:Normal
1:Standby
TST1
TST0
BCSC1
0
:Trig mode
1:HS pulse
TST2
0:Test
1
:Normal
BCWDTH
BCEDGE
0
:Rising
1:Falling
SWBLK
0
:Disable
1:Enable
BCSC0
0
:HS trig
1:BLK trig
BLKPOL
0
:Non-inv.
1:Inverted
0
:Normal
1:Test
ABLEN
0
:Bl. disable
1:Bl. enable
0
:Normal
1:Test
Reserved
0
1
09
Reserved
MOD
0
0
0
:DC
1:AC
0A
IBL1
1
0
0
0
0
0
0
0
0B
IBL2
1
0
0
0
0
0
0
0
0C
IBL3
1
0
0
0
0
0
0
0D
PASTBY
0
:Normal
1:Standby
VIP
0:0.2V
1
:0.4V
PBGEN
0
:Disable
1:Enable
PBVIVEN
0
:Disable
1:Enable
Reserved
TST4
TST3
BW
0
0
:Normal
1:Test
0
:Normal
1:Test
1
0
0
0
0E
IBOF
IBLRG
0:Wide
1
:Narrow
1
0
0
0
0
0
0F
PBINS
0
:PB Pin
1:Perman.
Reserved
PBCRST
Reserved
PBBRIG
0
0
1
0
0
1
10
PBVIVAM
Reserved
PBVIVTC
Reserved
0
1
0
1
0
0
0
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