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參數(shù)資料
| 型號： | STV9212 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Video Processor for CRT Monitors with PictureBooST |
| 中文描述： | 視頻處理器PictureBooST的CRT顯示器 |
| 文件頁數(shù)： | 22/34頁 |
| 文件大?。?/td> | 335K |
| 代理商： | STV9212 |
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I2C-Bus Interface Specifications
STV9212
22/34
Bits[6:5] = Test mode activation for device testing in
fabrication. When performing software
blanking through SWBLK bit, TST1bit
must be set to 1.
0: Normal operation mode (Default)
1: Test mode
Bits[4,0] = Blanking and clamping pulse source.
Bits[3:2] = Width of ICP pulse when bit BCSC1is 0.
Bit 1 = When HS pin is selected to trigger the ICP
pulse generator.
0: Trailing edge of HS pulse (Default)
1: Leading edge of HS pulse
When BLK pin is selected to trigger the ICP pulse
generator:
Refer to BLKPOL bit description.
Sad09
Read/Write
Reset Value: 0001 0000 (10h)
Bit 7 = Amplifier standby selection.
0: Normal (default)
1: Standby
Bit 6 = Amplifier blanking enable. The bit is “don’t
care” whenever bit
ASTBY
is in Standby
position.
0: Blanking pulse not generated (default)
1: Blanking pulse generated
Bit 5 = Reserved.
Bit 4 = Test mode activation for device testing in
fabrication.
0: Test mode
1: Normal operation mode (Default)
Bit 3 = Reserved.
Bit 2 = Application mode selection.
0: Application with DC-coupled cathodes.
(Default)
1: Application with AC-coupled cathodes.
Bit 1 = Permanent blanking of video channels
through software.
0: Disable, blanking gated with signal on
BLK pin. (Default)
1: Permanent blanking. Bit
TST1
must
also be set to 1.
Bit 0 = Blanking signal (H-fly back) polarity
inversion. For correct operation, the
internal BLKI pulse after this controlled
inversion must be positive.
0: Non Inverted, good for positive blanking
pulse (Default)
1: Inverted, good for negative blanking
pulse
Sad0A, Sad0B and Sad0C
Read/Write
Reset Value: 1000 0000 (80h)
Bits[7:0] = Infra-black (Cut-off) Level Control,
Channels 1 to 3
(IBLx)
In DC-coupling mode, the register controls
the pedestal of corresponding video
channel signal.
In AC-coupling mode, the register controls
the level on outputs CO1, CO2 or CO3,
respectively.
Sad0D
Read/Write
Reset Value: 0000 1000 (08h)
Bit 7 = Preamplifier and Amplifier STandBY
selection
0: Normal (default)
1: Standby
Bit 6 = Reserved.
BCSC1
BCSC0
Selected Source
0
0
1
0
1
HS pin trigger (Default)
BLK pin trigger
HS pin pulse
Don’t care
BCWDTH
BCPC Width
0
0
1
1
0
1
0
1
0.33 μs
0.66 μs (Default)
1 μs
1.33 μs
BCEDGE
BLKPOL
Trigger on BLK
0
0
1
1
0
1
0
1
Rising edge (default)
Falling edge
Falling edge
Rising edge
7
0
ASTB
Y
ABLE
N
TST2
MOD
SWBL
K
BLKP
OL
7
0
IBL1[7:0]
IBL2[7:0]
IBL3[7:0]
7
0
PAST
BY
TST[4:3]
BW[3:0]
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