- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25648 > STM32W108HBU7 (STMICROELECTRONICS) SPECIALTY MICROPROCESSOR CIRCUIT, QCC40 PDF資料下載
參數(shù)資料
| 型號(hào)： | STM32W108HBU7 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-40 |
| 文件頁數(shù)： | 71/198頁 |
| 文件大?。?/td> | 2871K |
| 代理商： | STM32W108HBU7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當(dāng)前第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁
Interrupts
STM32W108CB, STM32W108HB
162/198
Doc ID 16252 Rev 3
12
Interrupts
The STM32W108's interrupt system is composed of two parts: a standard ARM Cortex-
M3 Nested Vectored Interrupt Controller (NVIC) that provides top level interrupts, and an
Event Manager (EM) that provides second level interrupts. The NVIC and EM provide a
simple hierarchy. All second level interrupts from the EM feed into top level interrupts in the
NVIC. This two-level hierarchy allows for both fine granular control of interrupt sources and
coarse granular control over entire peripherals, while allowing peripherals to have their own
interrupt vector.
description of the NVIC and an overview of the exception table (ARM nomenclature refers to
interrupts as exceptions) and Section 12.2: Event manager provides a more detailed
description of the Event Manager including a table of all top-level peripheral interrupts and
their second-level interrupt sources.
In practice, top-level peripheral interrupts are only used to enable or disable interrupts for an
entire peripheral. Second-level interrupts originate from hardware sources, and therefore
are the main focus of applications using interrupts.
12.1
Nested vectored interrupt controller (NVIC)
The ARM Cortex-M3 Nested Vectored Interrupt Controller (NVIC) facilitates low-latency
exception and interrupt handling. The NVIC and the processor core interface are closely
coupled, which enables low-latency interrupt processing and efficient processing of late
arriving interrupts. The NVIC also maintains knowledge of the stacked (nested) interrupts to
enable tail-chaining of interrupts.
The ARM Cortex-M3 NVIC contains 10 standard interrupts that are related to chip and
CPU operation and management. In addition to the 10 standard interrupts, it contains 17
individually vectored peripheral interrupts specific to the STM32W108.
The NVIC defines a list of exceptions. These exceptions include not only traditional
peripheral interrupts, but also more specialized events such as faults and CPU reset. In the
ARM Cortex-M3 NVIC, a CPU reset event is considered an exception of the highest
priority, and the stack pointer is loaded from the first position in the NVIC exception table.
The NVIC exception table defines all exceptions and their position, including peripheral
interrupts. The position of each exception is important since it directly translates to the
location of a 32-bit interrupt vector for each interrupt, and defines the hardware priority of
exceptions. Each exception in the table is a 32-bit address that is loaded into the program
counter when that exception occurs. Table 33 lists the entire exception table. Exceptions 0
(stack pointer) through 15 (SysTick) are part of the standard ARM Cortex-M3 NVIC, while
exceptions 16 (Timer 1) through 32 (Debug) are the peripheral interrupts specific to the
STM32W108 peripherals. The peripheral interrupts are listed in greater detail in Table 34.
Table 33.
NVIC exception table
Exception
Position
Description
-
0
Stack top is loaded from first entry of vector table on reset.
Reset
1
Invoked on power up and warm reset. On first instruction, drops to
lowest priority (Thread mode). Asynchronous.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STP506C-2IW-012V | SINGLE COLOR DISPLAY CLUSTER, WHITE, 152.4 mm |
| SUGR47M | DUAL COLOR LED, RED/GREEN, 5 mm |
| SUR76D | SINGLE COLOR LED, RED, 3 mm |
| SUY17D | SINGLE COLOR LED, YELLOW, 3.9 mm |
| SY405T | SINGLE COLOR LED, AMBER, 2.7 mm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STM32WC-RFCKIT | 功能描述:Zigbee/802.15.4開發(fā)工具 STM32W Low-Cost RF STM32F103 MCU Kit RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:EM35x 頻率:2.4 GHz 接口類型:USB 工作電源電壓: |
| STM32W-RFCKIT | 功能描述:開發(fā)板和工具包 - 無線 STM32W RF CNTRL KIT STM32F103 USB JTAG RoHS:否 制造商:Arduino 產(chǎn)品:Evaluation Boards 工具用于評(píng)估:AT32UC3L 核心:AVR32 頻率: 接口類型:USB 工作電源電壓:5 V |
| STM3-3 | 制造商:RINO MECH.(GENGARELL 功能描述: |
| STM330 | 制造商:EnOcean GmbH 功能描述:Temperature energy harvester, 868MHz |
| STM330U | 制造商:EnOcean GmbH 功能描述:Temperature energy harvester, 315MHz 制造商:EnOcean GmbH 功能描述:Temperature energy harvester, 902MHz |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。