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參數(shù)資料
| 型號(hào)： | STM32W108HBU7 |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-40 |
| 文件頁(yè)數(shù)： | 63/198頁(yè) |
| 文件大?。?/td> | 2871K |
| 代理商： | STM32W108HBU7 |
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STM32W108CB, STM32W108HB
Analog-to-digital converter
Doc ID 16252 Rev 3
155/198
the regulator is factory trimmed to within 40 mV of 1.80 V. Offset and gain correction using
VREF or VDD_PADSA reduces both ADC gain errors and reference errors but it is limited by
the absolute accuracy of the supply. Correction using VREF is recommended because
VREF is calibrated by the ST HAL software against the factory-trimmed VDD_PADSA. The
ADC calibrates as a single-ended measurement. Differential signals require correction of
both their inputs.
enabled, respectively.
Equation notes
●
All N are 16-bit numbers.
●
NX is a sampling of the desired analog source.
●
NGND is a sampling of ground. Due to the ADC's internal design, ground does not yield
0x0000 as the conversion result. Instead, ground yields a value closer to 1/4 of the
maximum negative 2’s complement — for example, 0xC000 (-16384).
●
NVREF is a sampling of VREF. Due to the ADC's internal design, VREF does not yield
the maximum positive 2’s complement 0x7FFF (32767) as the conversion result.
Instead, VREF yields a value close to 1/4 of the maximum positive 2’s complement
when the input buffer is not selected (for example, 0x4000 (16384)) and yields a value
close to 1/4 of the maximum negative 2’s complement when the input buffer is selected
(for example, 0xC000 (-16384)).
●
NVREF/2 is a sampling of VREF/2. Due to of the ADC's internal design, VREF/2 yields a
value close to 0x0000 when the input buffer is not selected and yields a value closer to
3/8 of the maximum negative 2’s complement when the input buffer is selected (for
example, 0xA000 (-24576)).
●
NVDD_PADSA is a sampling of the regulated supply, VDD_PADSA/2.
●
<<16 indicates a bit shift left by 16 bits.
●
When calculating the voltage of VDD_PADSA (ADC_MUXn=11), V = (1/2) *
VDD_PADSA
Table 31 shows the equations used when the input buffer is disabled.
The equations in Table 31 cannot be applied when the input buffer is selected, as the
calibration signal GND is outside the voltage range of the buffer. Table 32 shows the
equations used when the input buffer is selected.
Table 31.
Offset and gain correction (ADC_HVSELn=0)
Calculation Type
Corrected Sample
Absolute Voltage
Offset corrected
Offset and gain corrected
using VREF, normalized to
VREF
Offset and gain corrected
using VDD_PADSA,
normalized to VDD_PADSA
)
(
GND
X
N
=
)
(
16
)
(
GND
VREF
GND
X
N
<<
=
16
2
)
(
VREF
N
V
×
=
)
(
2
16
)
(
_
GND
PADSA
VDD
GND
X
V
N
V
N
×
<<
=
14
2
)
_
(
PADSA
VDD
N
V
×
=
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