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參數(shù)資料
| 型號： | ST7PLITE15F1B6 |
| 廠商： | 意法半導體 |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI |
| 中文描述： | 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，4定時器，微控制器的SPI |
| 文件頁數(shù)： | 66/131頁 |
| 文件大小： | 2046K |
| 代理商： | ST7PLITE15F1B6 |
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ST7LITE1
66/131
1
LITE TIMER
(Cont’d)
11.3.3 Functional Description
11.3.3.1 Timebase Counter 1
The 8-bit value of Counter 1 cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of f
OSC
/32. An
overflow event occurs when the counter rolls over
from F9h to 00h. If f
OSC
= 8 MHz, then the time pe-
riod between two counter overflow events is 1 ms.
This period can be doubled by setting the TB bit in
the LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by
hardware and an interrupt request is generated if
the TB1IE bit is set. The TB1F bit is cleared by
software reading the LTCSR1 register.
11.3.3.2 Timebase Counter 2
Counter 2 is an 8-bit autoreload upcounter. It can
be read by accessing the LTCNTR register. After
an MCU reset, it increments at a frequency of
f
OSC
/32 starting from the value stored in the
LTARR register. A counter overflow event occurs
when the counter rolls over from FFh to the
LTARR reload value. Software can write a new
value at anytime in the LTARR register, this value
will be automatically loaded in the counter when
the next overflow occurs.
When Counter 2 overflows, the TB2F bit in the
LTCSR2 register is set by hardware and an inter-
rupt request is generated if the TB2IE bit is set.
The TB2F bit is cleared by software reading the
LTCSR2 register.
11.3.3.3 Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter (Counter 1) 1 after a rising
or falling edge is detected on the LTIC pin. When
an input capture occurs, the ICF bit is set and the
LTICR1 register contains the MSB of Counter 1.
An interrupt is generated if the ICIE bit is set. The
ICF bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
Figure 40. Input Capture Timing Diagram.
04h
8-bit COUNTER 1
t
01h
f
OSC
/32
xxh
02h
03h
05h
06h
07h
04h
LTIC PIN
ICF FLAG
LTICR REGISTER
CLEARED
BY S/W
READING
LTIC REGISTER
4μs
(@ 8MHz f
OSC
)
f
CPU
07h
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