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| 型號(hào)： | ST7PLITE15F1B6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI |
| 中文描述： | 8位單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，4定時(shí)器，微控制器的SPI |
| 文件頁(yè)數(shù)： | 56/131頁(yè) |
| 文件大?。?/td> | 2046K |
| 代理商： | ST7PLITE15F1B6 |
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ST7LITE1
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12-BIT AUTORELOAD TIMER
(Cont’d)
11.2.3 Functional Description
PWM Mode
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins. The PWMx output signals can be enabled or
disabled using the OEx bits in the PWMCR regis-
ter.
PWM Frequency and Duty Cycle
The four PWM signals have the same frequency
(f
PWM
) which is controlled by the counter period
and the ATR register value.
f
PWM
= f
COUNTER
/ (4096 - ATR)
Following the above formula,
– If f
COUNTER
is 32 MHz, the maximum value of
f
PWM
is 8 MHz (ATR register value = 4092), the
minimum value is 8 KHz (ATR register value = 0)
– If f
COUNTER
is 4 Mhz
,
the maximum value of f
PWM
is 2 MHz (ATR register value = 4094),the mini-
mum value is 1 KHz (ATR register value = 0).
Note:
The maximum value of ATR is 4094 be-
cause it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
When a upcounter overflow occurs (OVF event),
the preloaded Duty cycle values are transferred to
the Duty Cycle registers and the PWMx signals
are set to a high level. When the upcounter match-
es the DCRx value the PWMx signals are set to a
low level. To obtain a signal on a PWMx pin, the
contents of the corresponding DCRx register must
be greater than the contents of the ATR register.
The polarity bits can be used to invert any of the
four output signals. The inversion is synchronized
with the counter overflow if the TRAN bit in the
TRANCR register is set (reset value). See
Figure
34
.
Figure 34. PWM Inversion Diagram
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (4096 - ATR)
Note
: To get the maximum resolution (1/4096), the
ATR register must be 0. With this maximum reso-
lution, 0% and 100% can be obtained by changing
the polarity.
Figure 35. PWM Function
PWMx
PWMx
PIN
counter
overflow
OPx
PWMxCSR Register
inverter
DFF
TRAN
TRANCR Register
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ATR)
P
t
4095
000
WITH OE=1
AND OPx=0
WITH OE=1
AND OPx=1
C
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