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參數(shù)資料
| 型號： | ST7PLITE15F1B6 |
| 廠商： | 意法半導體 |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI |
| 中文描述： | 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，4定時器，微控制器的SPI |
| 文件頁數(shù)： | 38/131頁 |
| 文件大小： | 2046K |
| 代理商： | ST7PLITE15F1B6 |
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ST7LITE1
38/131
1
9 POWER SAVING MODES
9.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the ST7 (see
Figure 20
):
■
Slow
■
Wait (and Slow-Wait)
■
Active Halt
■
Auto Wake up From Halt (AWUFH)
■
Halt
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(f
OSC2
).
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 20. Power Saving Mode Transitions
9.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
CPU
) to
the available supply voltage.
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
lower frequency.
Note
: SLOW-WAIT mode is activated when enter-
ing WAIT mode while the device is already in
SLOW mode.
Figure 21. SLOW Mode Clock Transition
POWER CONSUMPTION
WAIT
SLOW
RUN
ACTIVE HALT
High
Low
SLOW WAIT
AUTO WAKE UP FROM HALT
HALT
SMS
f
CPU
NORMAL RUN MODE
REQUEST
f
OSC
f
OSC
/32
f
OSC
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